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PDF FDMA86151L Data sheet ( Hoja de datos )
| Número de pieza | FDMA86151L | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2014
FDMA86151L
Single N-Channel PowerTrench® MOSFET
100 V, 3.3 A, 88 mΩ
Features
Max rDS(on) = 88 mΩ at VGS = 10 V, ID = 3.3 A
Max rDS(on) = 132 mΩ at VGS = 4.5 V, ID = 2.7 A
Low Profile - 0.8 mm maximum in the new package MicroFET
2x2 mm
Free from halogenated compounds and antimony oxides
RoHS Compliant
General Description
This device has been designed to provide maximum efficiency
and thermal performance for synchronous buck converters. The
low rDS(on) and gate charge provide excellent switching
performance.
Application
DC – DC Buck Converters
Pin 1
Drain
DD G
Source
Bottom Drain Contact
DD
DD
DD S
MicroFET 2X2 (Bottom View)
G
S
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Curre -Continuous
-Pulsed
TA = 25 °C
Power Dissipation
TA = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 3)
(Note 1a)
(Note 1b)
Ratings
100
±20
3.3
20
2.4
0.9
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
52
145
°C/W
Device Marking
151
Device
FDMA86151L
Package
MicroFET 2X2
Reel Size
7”
Tape Width
8 mm
Quantity
3000 units
©2014 Fairchild Semiconductor Corporation
FDMA86151L Rev.C
1
www.fairchildsemi.com
1 page  
Dimensional Outline and Pad Layout
0.15 C
2X
2. 00
A
B
PIN #1 LOCATION
2.00
TOP VIEW
0.15 C
2X
0.8 MAX
0.10 C
0.08 C 0.05
0.00
S EA TING
P LA NE
(0.20)
SIDE VIEW
C
PIN #1 IDENT
6X
0.33
0.20
(0.50)
1.00
0.80
1
(0.15)
(0.50)
(0.30)
3 0.66
0.56
1.05
0.95
6
0.65
1.30
4
0.35
0.25
6X
0.10 C A B
0.05 C
BOTTOM VIEW
1.00
6
(0.20)
4
No Traces or Vias
Allowed in this Area
1.05
(0.48)
1
0.65 TYP
1.35
2.30
3
0.40 TYP
RECOMMENDED LAND PATTERN OPT 1
1.00
6
(0.45)
(0.20)
4
1.05
(0.48)
1
0.65 TYP
1.35
0.66 2.30
3
0.40 TYP
RECOMMENDED LAND PATTERN OPT 2
A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION
MO-229 DATED AUG/2003
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. DRAWING FILENAME: MKT-MLP06Prev1.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
https://www.fairchildsemi.com/evaluate/package-specifications/packageDetails.html?id=PN_MLDEB-CC6
©2014 Fairchild Semiconductor Corporation
FDMA86151L Rev.C
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet FDMA86151L.PDF ] | |
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