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PDF FDMC8588DC Data sheet ( Hoja de datos )
| Número de pieza | FDMC8588DC | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FDMC8588DC
N-Channel Dual CoolTM 33 PowerTrench® MOSFET
25 V, 40 A, 5.7 mΩ
February 2016
Features
General Description
Dual CoolTM Top Side Cooling PQFN package
Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 17 A
State-of-the-art switching performance
Lower output capacitance, gate resistance, and gate charge
boost efficiency
Shielded gate technology reduces switch node ringing and
increases immunity to EMI and cross conduction
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency and to minimize switch node
ringing of DC/DC converters using either synchronous or
conventional switching PWM controllers. It has been optimized
for low gate charge, low rDS(on), fast switching speed and body
diode reverse recovery performance.
Applications
High side switching for high end computing
RoHS Compliant
High power density DC-DC synchronous buck converter
Pin 1
G
S
S
S
S
S
D
D
Pin 1
D
D
D
D
Top
Dual CoolTM 33
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
- Continuous (Package limited) TC = 25 °C
- Continuous (Silicon Limited) TC = 25 °C
- Continuous
EAS
PD
TJ, TSTG
- Pulsed
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
S
G
(Note 5)
(Note 4)
(Note 1a)
(Note 3)
(Note 1a)
D
D
Ratings
25
±12
40
73
17
60
29
41
3.0
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJC
RθJA
RθJA
RθJA
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Top Source)
(Bottom Drain)
(Note 1a)
(Note 1b)
(Note 1i)
(Note 1j)
(Note 1k)
7.0
3.0
42
105
17
26
12
°C/W
Device Marking
08DC
Device
FDMC8588DC
Package
Dual CoolTM 33
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
1
www.fairchildsemi.com
1 page  
Typical Characteristics TJ = 25°C unless otherwise noted
4.5
ID = 17 A
3.6
2.7
1.8
VDD = 10 V
VDD = 13 V
VDD = 15 V
0.9
0.0 0
369
Qg, GATE CHARGE (nC)
12
15
Figure 7. Gate Charge Characteristics
50
3000
1000
Ciss
Coss
100 Crss
f = 1 MHz
VGS = 0 V
30
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
80
10
TJ = 25 oC
TJ = 125 oC
TJ = 100 oC
60 VGS = 10 V
40
Limited by Package
20 RθJC = 3.0 oC/W
VGS = 4.5 V
01.001
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100 1000
10 100 μs
1 THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 105 oC/W
TA = 25 oC
0.01
0.01
0.1
1
1 ms
10 ms
100 ms
1s
10 s
DC
10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
100
10
SINGLE PULSE
RθJA = 105 oC/W
1 TA = 25 oC
0.5
10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
5
www.fairchildsemi.com
5 Page | ||
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| PDF Descargar | [ Datasheet FDMC8588DC.PDF ] | |
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