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PDF MT5C1009 Data sheet ( Hoja de datos )
| Número de pieza | MT5C1009 | |
| Descripción | 128K x 8 SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MT5C1009 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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SRAM
MT5C1009
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
FEATURES
• Access Times: 12, 15, 20, 25, 35, 45, 55 and 70 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-12 (IT only)
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
C
CW
EC
ECA
F
DCJ
SOJ
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.micross.com
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CNEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin Flat Pack (F)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 NCEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin LCC (ECA)
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS 16
32 VCC
31 A15
30 NCEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
29 WE \
28 A13
27 A8
26 A9
25 A11
24 OE \
23 A10
22 CE1\
21 DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory applica-
tions, this device offers chip enable (CE\) and output enable
(OE\) features. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is ac-
complished when WE\ remains HIGH and CE\ and OE\ go
LOW. The devices offer a reduced power standby mode when
disabled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode,
reducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
SRAM
MT5C1009
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
Q
Q
30
255
480
5 pF
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width < 20ns
3. I is dependent on output loading and cycle rates.
CC
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE and tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL MIN MAX
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
* Low Power, -20 device only
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V
VDR
VCC = 2V
ICCDR1*
ICCDR2
tCDR
tR
2
0
tRC
---
0.75
1.0
---
UNITS NOTES
V
mA
mA
ns 4
ns 4, 11
MT5C1009
Rev. 6.2 01/10
LOW Vcc DATA RETENTION WAVEFORM
VCC
CE1\
VIH
VIL
tCDR
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
tR
VDR DON’T CARE
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
SRAM
MT5C1009
MECHANICAL DEFINITIONS*
Micross Case #208 (Package Designator ECA)
SMD 5962-89598, Case Outline M
D1
L1
E E1
e
See Detail A
A
DL
Detail A
B1
b1
b2
*All measurements are in inches.
MT5C1009
Rev. 6.2 01/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MT5C1009.PDF ] | |
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