|
|
PDF MT4C4001J Data sheet ( Hoja de datos )
| Número de pieza | MT4C4001J | |
| Descripción | 1 MEG x 4 DRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT4C4001J (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
DRAM
MT4C4001J
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR),
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
• Timing
70ns access
80ns access
MARKING
-7
-8
PIN ASSIGNMENT
(Top View)
20-Pin DIP (C, CN)
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
20 Vss
19 DQ4
18 DQ3
17 CAS\
16 OE\
15 A8
14 A7
13 A6
12 A5
11 A4
20-Pin DIP (CZ)
20-Pin SOJ (ECJ,ECJA),
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
DQ1
DQ2
WE\
RAS\
A9
1
2
3
4
5
A0 9
A1 10
A2 11
A3 12
Vcc 13
26 Vss
25 DQ4
24 DQ3
23 CAS\
22 OE\
18 A8
17 A7
16 A6
15 A5
14 A4
OE\ 1
DQ3 3
Vss 5
DQ2 7
RAS\ 9
A0 11
A2 13
Vcc 15
A5 17
A7 19
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
100ns access
120ns access
-10
-12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state memory
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC*
Ceramic ZIP
Ceramic SOJ
Ceramic SOJ w/ Cu J-lead
Ceramic Gull Wing
CN
C
ECN
CZ
ECJ
ECJA
ECG
No. 103
No. 104
No. 202
No. 400
No. 504
No. 504A
No. 600
containing 4,194,304 bits organized in a x4 configuration. Dur-
ing READ or WRITE cycles each bit is uniquely addressed
through the 20 address bits which are entered 10 bits (A0-
A9) at a time. RAS\ is used to latch the first 10 bits and CAS\
the later 10 bits. A READ or WRITE cycle is selected with
the WE\ input. A logic HIGH on WE\ dictates READ mode
while a logic LOW on WE\ dictates WRITE mode. During a
WRITE cycle, data-in (D) is latched by the falling edge of WE\
or CAS\, whichever occurs last. If WE\ goes LOW prior to
CAS\ going LOW, the output pin(s) remain open (High-Z) until
*NOTE: If solder-dip and lead-attach is desired on LCC pack- the next CAS\ cycle. If WE\ goes LOW after data reaches the
ages, lead-attach must be done prior to the solder-dip opera- output pin(s), Qs are activated and retain the selected cell data
tion. as long as CAS\ remains low (regardless of WE\ or RAS\).
This LATE WE\ pulse results in a READ-WRITE cycle. The
For more products and information
please visit our web site at
www.micross.com
four data inputs and four data outputs are routed through four
pins using common I/O and pin direction is controlled by WE\
and OE\. FAST-PAGE-MODE operations allow faster data
operations (READ, WRITE, or READ-MODIFY-WRITE)
within a row address (A0-A9) defined page boundary. The
FAST PAGE MODE
(continued)
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
DRAM
MT4C4001J
CAPACITANCE
PARAMETER
Input Capacitance: A0-A10
Input Capacitance: RAS\, CAS\, WE\, OE\
Input/Output Capacitance: DQ
SYM
CI1
CI2
CIO
MIN
MAX
7
7
8
UNITS
pF
pF
pF
NOTES
2
2
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%)
PARAMETER
Random READ or WRITE cycle time
READ-WRITE cycle time
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
Access time from CAS\ precharge
RAS\ pulse width
RAS\ pulse width (FAST PAGE MODE)
RAS\ hold time
RAS\ precharge time
CAS\ pulse width
CAS\ hold time
CAS\ precharge time
CAS\ precharge time (FAST PAGE MODE)
RAS\ to CAS\ delay time
CAS\ to RAS\ precharge time
Row address setup time
Row address hold time
RAS\ to column address delay time
Column address setup time
Column address hold time
Column address hold time (referenced to RAS\)
Column address to RAS\ lead time
Read command setup time
Read command hold time (referenced to CAS\)
Read command hold time (referenced to RAS\)
CAS\ to output in Low-Z
Output buffer turn-off delay
WE\ command setup time
SYM
tRC
tRWC
tPC
tPRWC
tRAC
tCAC
tAA
tCPA
tRAS
tRASP
tRSH
tRP
tCAS
tCSH
tCPN
tCP
tRCD
tCRP
tASR
tRAH
tRAD
tASC
tCAH
tAR
tRAL
tRCS
tRCH
tRRH
tCLZ
tOFF
tWCS
-7
MIN MAX
130
180
40
90
70
20
35
35
70 10,000
70 100,000
20
50
20 10,000
70
10
10
20 50
5
0
10
15 35
0
15
50
35
0
0
0
0
0 20
0
-8
MIN MAX
150
200
45
90
80
20
40
40
80 10,000
80 100,000
20
60
20 10,000
80
10
10
20 60
5
0
10
15 40
0
15
60
40
0
0
0
0
0 20
0
-10
MIN MAX
190
240
55
110
90
25
45
45
100 10,000
100 100,000
25
70
25 10,000
100
12
12
25 75
5
0
15
20 50
0
20
70
50
0
0
0
0
0 20
0
-12
MIN MAX
220
255
70
140
120
30
60
60
120 100,000
120 100,000
30
90
30
120
15
15
25 90
10
0
15
20 60
0
25
85
60
0
0
0
0
0 20
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
14
15
16
17
18
19
19
20
21, 27
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
RAS\-ONLY REFRESH CYCLE
(ADDR = A0-A9; WE\ = Don’t Care)
DRAM
MT4C4001J
CAS\-BEFORE-RAS\ REFRESH CYCLE
(A0-A9, and OE\ = DON’T CARE)
HIDDEN REFRESH CYCLE24
(WE\ = HIGH, OE\ = LOW)
MT4C4001J
Rev. 2.3 03/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MT4C4001J.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT4C4001 | standard or self refresh |  Micron Technology |
| MT4C4001J | 1 MEG x 4 DRAM | Micross |
| MT4C4001J | 1 MEG x 4 DRAM Fast Page Mode DRAM |  Austin Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |