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PDF AS8FLC2M32 Data sheet ( Hoja de datos )
| Número de pieza | AS8FLC2M32 | |
| Descripción | Multi-Chip Module | |
| Fabricantes | Micross | |
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FLASH
AS8FLC2M32
Hermetic, Multi-Chip Module
(MCM)
64Mb, 2M x 32, 3.3Volt Boot Block FLASH Array
FIGURE 1: PIN ASSIGNMENT
(Top View)
Available via Applicable Specifications:
• MIL-PRF-38534, Class H
• DSCC SMD 5962-08245
FEATURES
• 64Mb device, total density, organized as 2M x 32
• Bottom Boot Block (Sector) Architecture
(Contact factory for top boot)
• Operation with single 3.0V Supply
• Available in multiple Access time variations
• Individual byte control via individual byte selects (CSx\)
• Low Power CMOS
• 1,000,000 Erase/Program Cycles
• Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
• Sector Architecture:
• One 16K byte, two 8K byte, one 32K byte and
thirty-one 64Kbyte sectors (byte mode)
• Any combination of sectors can be concurrently erased
• MCM supports full array (multi-chip) Erase
• Embedded Erase and Program Algorithms
• Erase Suspend/Resume; Supports reading data from or
programming data to a sector not being Erased
• TTL Compatible Inputs and Outputs
• Military and Industrial operating temperature ranges
OPTION
Access Speed
70ns*
90ns
100ns
120ns
*Contact Factory
Package
Ceramic Quad Flat Pack
Ceramic Hex Inline Pack
MARKING
-70
-90
-100
-120
Q
P
Temperature Range
Full Mil (MIL-PRF-38534, Class H /Q
Military Temp (-55oC to +125oC) /XT
Industrial (-40oC to +85oC)
/IT
For more products and information
please visit our web site at
www.micross.com
ID/OQ00
10
60
ID/OQ11
11
59
ID/0Q22
12
78
ID/OQ33
ID/OQ44
13
14
57
76
ID/OQ55
ID/OQ6
15
16
55
54
ID/OQ77
17
53
GND
18
52
ID/OQ88
19
51
ID/OQ99
20
50
DI/QO1100
21
49
DI/QO1111 22 [Package Designator QT] 48
DI/0Q1122
23
47
DI/QO1133
24
46
DI/OQ1144
DI/OQ1155
25
26
45
44
DI/QO1166
DI/QO1177
DI/QO1188
DI/OQ19
DI/QO2200
DI/QO2211
DI/QO2222
DI/QO2233
GND
DI/QO2244
DI/OQ25
DI/QO2266
DI/QO2277
DI/QO2288
DI/OQ29
DI/QO3300
DI/OQ31
Pin Assignment
(Top View)
ID/OQ88 Reset\ ID/OQ15
ID/OQ24 VCC ID/OQ331
ID/OQ99 CS2\ DI/QO144
ID/OQ225 CS4\ DI/OQ30
DI/OQ100 GND DI/QO133
DI/OQ266
NC ID/OQ29
A14 DI/OQ111 DI/OQ122
A7 ID/OQ27 ID/OQ28
A16 A10 OE\
A12 A4 A1
A11 A9 A17 66 HIP AN2C0 A5 A2
A0 A15 WE\
A13 A6 A3
A18 VCC ID/OQ77
A8 NC ID/OQ223
ID/OQ0 CS1\ DI/OQ6
ID/OQ16 CS3\ DI/OQ22
DI/QO11 A19 DI/OQ5
DI/OQ177 GND ID/OQ21
ID/OQ2 DI/QO33 DI/OQ4
DI/QO188 DI/OQ19 DI/OQ200
[Package Designator PH]
GENERAL DESCRIPTION
The AS8FLC2M32B is a 64Mb FLASH Multi-Chip Module
organized as 2M x 32 bits. The module achieves high speed
access, low power consumption and high reliability by employ-
ing advanced CMOS memory technology. The military grade
product is manufactured in compliance to the MIL-PRF-38534
specifications, making the AS8FLC2M32B ideally suited for
military or space applications. The module is offered in a
68-lead 0.990 inch square ceramic quad flat pack or 66-lead
1.185inch square ceramic Hex In-line Package (HIP). The
CQFP package design is targeted for those applications, which
require low profile SMT Packaging.
AS8FLC2M32B
Rev. 1.6 05/11
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
FLASH
AS8FLC2M32
Autoselect Code Table
PROGRAM or ERASE operation is not executing, the RESET
operation is completed within a time of tREADY. The system
can read data tRH after the RESET\ pin returns to VIH.
Refer to the “AC Characteristics” tables for RESET\
parameters.
identification, and sector protection verification through
identifier codes output via the appropriate Byte DQ’s. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the
command register.
Output Disable Mode
When the OE\ input is at VIH, output from the device is
disabled. The output pins are placed in the high Impedance
State.
Autoselect Mode
The autoselect mode provides manufacturer and device
When using programming equipment (modified to support
multi-byte devices, or supplied from the programming
equipment provider as such), the autoselect mode requires
VID (11.5v to 12.5v) on address pin A9. Address pins A6,
A1, and A0 must be as shown in the Autoselect Table below.
In addtion, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits. When
all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on
the appropriate Byte DQ’s.
To access the autoselect codes in-system, the host system can
issue the autoselect command via the command register.
AS8FLC2M32B
Rev. 1.6 05/11
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
FLASH
AS8FLC2M32
Any commands WRITTEN to the chip during the Embedded
ERASE operation are ignored. Note that a HARDWARE
RESET during the chip erase operation immediately terminates
the operation. The CHIP ERASE command sequence should
be reinitiated once the device has returned to READING Array
data, to ensure data integrity.
When the Embedded Erase Algorithm is complete, the device
returns to READING Array data and addresses are no longer
latched. The system can determine the status of the ERASE
operation by using DQ2, DQ6, and DQ7 of Byte 1; DQ10, DQ14
and DQ15 of Byte 2; DQ18, DQ22 and DQ23 of Byte 3 as well
as DQ26, DQ30 and DQ31 of Byte 4.
The system can determine the status of the erase operation
by using byte data from each of the four bytes. When the
Embedded ERASE Algorithm is complete, the device returns to
READING Array data and Addresses are no longer latched.
Sector Erase Command Sequence
SECTOR ERASE is a six-bus cycle operation. The SECTOR
ERASE command sequence is initiated by WRITING two
UNLOCK cycles, followed by a SET-UP command. Two
additional UNLOCK WRITE cycles are then followed by the
address of the sector to be ERASED, and the SECTOR ERASE
command.
Erase Suspend/Erase Resume Commands
The ERASE SUSPEND command allows the system to interrupt
a SECTOR ERASE operation and then READ data from, or
PROGRAM data to, any sector not selected for ERASURE. This
command is valid only during the SECTOR ERASE command
sequence. The ERASE SUSPEND command is ignored if
WRITTEN during the CHIP ERASE operation or Embedded
Program algorithm. WRITING the ERASE SUSPEND
command during the SECTOR ERASE time-out immediately
terminates the time-out period and SUSPENDS the ERASE
operation. Addresses are “don’t-cares” when WRITING the
ERASE SUSPEND command.
The device does not require the system to PREPROGRAM the
memory prior to ERASE. The Embedded ERASE Algorithm
automatically PROGRAMS and verifies the sector for an all
zero data pattern prior to electrical ERASE. The system is
not required to provide any controls or timings during these
operations.
When the ERASE command is WRITTEN during a SECTOR
ERASE operation, the device requires a maximum of 20us to
SUSPEND the ERASE operation. However, when the ERASE
SUSPEND command is WRITTEN during the SECTOR ERASE
time-out, the device immediately terminates the time-out period
and SUSPENDS the ERASE operation.
After the command sequence is WRITTEN, a SECTOR ERASE
time-out of 50uS begins. During the time-out period, additional
Sector Addresses and SECTOR ERASE commands may be
WRITTEN. Loading the SECTOR ERASE buffer may be
done in any sequence and the number of sectors may be from
one sector to all sectors. The time between these additional
cycles must be less than 50uS, otherwise the last address and
command might not be accepted, and erasure may begin. It
is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last SECTOR ERASE command is
WRITTEN. If the time between additional SECTOR ERASE
commands can be assumed to be less than 50uS, the system
need not monitor DQ3, DQ11, DQ19 or DQ27 to determine
if the SECTOR ERASE has timed out. The time-out begins
from the rising edge of the final WEx\ pulse in the command
sequence.
Once the SECTOR ERASE operation has begun, only the
ERASE SUSPEND command is valid. All other commands
are ignored. Note that a HARDWARE RESET during the
SECTOR ERASE operation immediately terminates the op-
eration. The SECTOR ERASE command sequence should be
reinitiated once
After the ERASE operation has been SUSPENDED, the system
can READ Array data from or PROGRAM data to any sector not
selected for ERASURE. Normal READ and WRITE timings and
command definitions apply. READING at any Address within
ERASE-SUSPENDED sectors produces status data on three DQ
pins within each Byte. DQ2, DQ6, and DQ7 of Byte 1; DQ10,
DQ14 and DQ15 of Byte 2; DQ18, DQ22 and DQ23 of Byte 3
as well as DQ26, DQ30 and DQ31 of Byte 4 to determine if a
sector is actively ERASING or is ERASE-SUSPENDED.
After and ERASE-SUSPENDED program operation is complete,
the system can once again READ from or WRITE to within non-
suspended sectors. The system can determine the status of the
PROGRAM operation using the DQ6, 7 bits of Byte 1; DQ14,
15 of Byte 2; DQ22, 23 of Byte 3 and DQ30, 31 of Byte 4; just
as in the standard PROGRAM operation.
The system may also write the auto select command sequence
when the device is in the ERASE SUSPEND mode. The device
allows READING autoselect codes even at addresses within
AS8FLC2M32B
Rev. 1.6 05/11
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AS8FLC2M32.PDF ] | |
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