PDF AS4DDR264M72PBG1 Data sheet ( Hoja de datos )

Número de pieza	AS4DDR264M72PBG1
Descripción	4.8 Gb SDRAM-DDR2
Fabricantes	Micross
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No Preview Available ! iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • Proprietary Enchanced Die Stacked iPEM • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm • 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.1V common core power and I/O supply Programmable CAS latency: 3, 4, 5, 6 or 7 Posted CAS additive latency: 0, 1, 2, 3, 4 or 5 Write latency = Read latency - 1* tCK Organized as 64M x 72 Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical BENEFITS 61% Space Savings 55% I/O reduction vs Individual package approach Reduced part count Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 128M x 72 density in future Pin/Function equivalent to White W3H64M72E-xBSx ConfigurationAddressing Parameter Configuration RefreshCount RowAddress BankAddress ColumnAddress 64Megx72 8Megx16x8Banks 8K A0ͲA12(8k) BA0ͲBA2(8) A0ͲA9(1K) NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only FUNCTIONAL BLOCK DIAGRAM Ax, BA0-2 ODT VRef VCC VSS VSSQ CS\ WE\ RAS\ CAS\ CKE\ ODT UDMx, LDMx UDSQx,UDSQx\ LDSQx, LDSQx\ CKx,CKx\ A VCCQ VSSQ VCCL VSSDL A 2 2 2 2 DQ0-15 B VCCQ VSSQ VCCL VSSDL VCCQ VSSQ VCCL B VSSDL VCCQ VSSQ VCCL C VSSDL VCCQ VSSQ VCCL D VSSDL 2 2 2 2 DQ16-31 C 2 2 2 2 DQ32-47 D 2 2 2 2 2 2 2 DQ48-63 ODT LDM4 UDM4 DQ64-71 AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or speciﬁcations without notice. 1 1 page FIGURE 4 - POWER-UP AND INITIALIZATION Notes appear on page 7 iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 VDD VVDDDDQL VTT1 tVTD1 VREF T0 tCK CK# CK tCL tCL CKE LLVOCWMLOESVEL2 SLSOTWL_1LE8VEL2 ODT Command3 DM15 Ta0 Tb0 Tc0 Td0 Te0 Tf0 Tg0 Th0 Ti0 Tj0 Tk0 Tl0 Tm0 NOP4 PRE LM5 LM6 LM7 LM8 PRE9 REF10 REF LM11 LM12 LM13 Valid16 Address3 A10 = 1 Code Code Code Code A10 = 1 Code Code Code Valid DQS15 DQ15 RTT High-Z High-Z High-Z T = 200µs (MIN) Power-up: VDD and stable clock (CK, CK#) T = 400ns (MIN)16 tRPA tMRD tMRD tMRD EMR(2) EMR(3) EMR tMRD MR with DLL RESET tRPA tRFC tRFC tMRD tMRD tMRD See note 17 MR without EMR with DLL RESET OCD default EMR with OCD exit 200 cycles of CK are required before a READ command can be issued. Normal operation Indicates a break in time scale Don’t care AS4DDR264M72PBG1 Rev. 3.1 01/10 Micross Components reserves the right to change products or speciﬁcations without notice. 5 5 Page iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 DLL ENABLE/DISABLE The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 7. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using an LM command. The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued, to allow time for the internal clock to synchronize with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. OUTPUT DRIVE STRENGTH The output drive strength is deﬁned by bit E1, as shown in Figure 7. The normal drive strength for all outputs are speciﬁed to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 45-60 percent of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or point-to-point environments. DQS# ENABLE/DISABLE The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single ended mode and the DQS# ball is disabled. When disabled, DQS# should be left ﬂoating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is deﬁned by bit E12, as shown in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, thus removing output buffer current. The output disable feature is intended to be used during ICC characterization of read current. ON-DIE TERMINATION (ODT) ODT effective resistance, RTT (EFF), is deﬁned by bits E2 and E6 of the EMR, as shown in Figure 7. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is elected by enabling switch “sw1,” which enables all R1 values that are 150Ω each, enabling an effective resistance of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values of 100Ω enabling effective resistance of 50Ω Reserved states should not be used, as unknown operation or incompatibility with future versions may result. The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge powerdown modes of operation. ODT must be turned off prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until issuing the EMR command to enable the ODT feature, at which point the ODT ball will determine the RTT(EFF) value. Any time the EMR enables the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See “ODT Timing” section for ODT timing diagrams. AS4DDR264M72PBG1 Rev. 3.1 01/10 11 Micross Components reserves the right to change products or speciﬁcations without notice. 11 Page

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