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PDF AD9554-1 Data sheet ( Hoja de datos )
| Número de pieza | AD9554-1 | |
| Descripción | Multiservice Line Card Adaptive Clock Translator | |
| Fabricantes | Analog Devices | |
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Data Sheet
Quad PLL, Quad Input, Multiservice Line
Card Adaptive Clock Translator
AD9554-1
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually no
disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and
ITU-T G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Quad digital phase-locked loop (DPLL) architecture with four
reference inputs (single-ended or differential)
4 × 4 crosspoint allows any reference input to drive any PLL
Input reference frequencies from 2 kHz to 1000 MHz
Reference validation and frequency monitoring: 2 ppm
Programmable input reference switchover priority
20-bit programmable input reference divider
4 differential clock outputs with each differential pair
configurable as HCSL, LVDS-compatible, or LVPECL-
compatible
Output frequency range: 430 kHz to 941 MHz
Programmable 18-bit integer and 24-bit fractional feedback
divider in digital PLL
Programmable loop bandwidths from 0.1 Hz to 4 kHz
56-lead (8 mm × 8 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and synchronous digital hierarchy (SDH) to optical
transport network (OTN) mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Cable infrastructure
Data communications
Professional video
GENERAL DESCRIPTION
The AD9554-1 is a low loop bandwidth clock translator that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9554-1 generates an output clock synchronized to up to four
external input references. The digital PLLs (DPLLs) allow
reduction of input time jitter or phase noise associated with the
external references. The digitally controlled loop and holdover
circuitry of the AD9554-1 continuously generates a low jitter
output clock even when all reference inputs have failed.
The AD9554-1 operates over an industrial temperature range of
−40°C to +85°C. The AD9554 is a version of this device with
two outputs per PLL. If a single or dual DPLL version of this
device is needed, refer to the AD9557 or AD9559, respectively.
STABLE
SOURCE
FUNCTIONAL BLOCK DIAGRAM
STATUS AND
CONTROL PINS
REFERENCE
INPUT
MONITOR
AND MUX
CLOCK
MULTIPLIER
SERIAL INTERFACE
(SPI OR I2C)
DIGITAL
PLL0
DIGITAL
PLL1
DIGITAL
PLL2
DIGITAL
PLL3
ANALOG
PLL0
ANALOG
PLL1
ANALOG
PLL2
ANALOG
PLL3
÷3 TO ÷11
P0 DIVIDER
÷3 TO ÷11
P1 DIVIDER
÷3 TO ÷11
P2 DIVIDER
÷3 TO ÷11
P3 DIVIDER
AD9554-1
Figure 1.
Q0_B DIVIDER
Q1_B DIVIDER
Q2_B DIVIDER
Q3_B DIVIDER
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9554-1
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 1.8 V, TA = 25°C, unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE FOR 1.8 V OPERATION
VDD_SP
VDD
SUPPLY VOLTAGE FOR 1.5 V OPERATION
VDD_SP
VDD
Min Typ Max
1.47 1.8
1.71 1.8
2.625
1.89
1.47 1.5
1.47 1.5
2.625
1.53
Unit
V
V
V
V
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Table 1. The test conditions for
the typical (typ) supply current are at the typical supply voltage found in Table 1. The test conditions for the minimum (min) supply
current are at the minimum supply voltage found in Table 1.
Table 2.
Parameter
SUPPLY CURRENT FOR TYPICAL CONFIGURATION
IVDD_SP
IVDD
SUPPLY CURRENT FOR ALL BLOCKS RUNNING CONFIGURATION
IVDD_SP
IVDD
Min Typ Max Unit Test Conditions/Comments
Typical values are for the Typical
Configuration parameter
listed in Table 3; valid for both 1.5 V and 1.8 V
operation
0.01 0.04 0.1 mA
450 513 560 mA
Maximum values are for the All Blocks
Running parameter
listed in Table 3; valid for both 1.5 V and 1.8 V
operation
0.01 0.04 0.1 mA
450 566 650 mA
Rev. B | Page 5 of 99
5 Page 
Data Sheet
AD9554-1
TIME DURATION OF DIGITAL FUNCTIONS
Table 9.
Parameter
TIME DURATION OF DIGITAL FUNCTIONS
Power-Down Exit Time
Min Typ
51
Mx Pin to RESET Rising Edge Setup Time
Mx Pin to RESET Rising Edge Hold Time
RESET Falling Edge to Mx Pin High-Z Time
Max Unit Test Conditions/Comments
ms Time from power-down exit to system clock stable (including
the system clock stability timer default of 50 ms); does not
include time to validate input references or lock the DPLL
1 ns Mx refers to the M0, M1, M2, M3, M5, M6, M7 pins
1 ns
10 ns
DIGITAL PLL (DPLL_0, DPLL_1, DPLL_2, AND DPLL_3)
Table 10.
Parameter
Min Typ Max Unit
Test Conditions/Comments
DIGITAL PLL
Phase Frequency Detector (PFD) 2
Input Frequency Range
200 kHz
Loop Bandwidth
0.1
4000 Hz
Programmable design parameter; note that (fPFD/loop bandwidth) ≥ 50
Phase Margin
45 89 Degrees Programmable design parameter
Closed Loop Peaking
<0.1
dB Programmable design parameter; part can be programmed for
<0.1 dB peaking in accordance with Telcordia GR-253-CORE jitter transfer
ANALOG PLL (APLL_0, APLL_1, APLL_2, AND APLL_3)
Table 11.
Parameter
ANALOG PLL0 (APLL_0)
VCO Frequency Range
Phase Frequency Detector (PFD)
Input Frequency Range
Loop Bandwidth
Phase Margin
ANALOG PLL1 (APLL_1)
VCO Frequency Range
Phase Frequency Detector (PFD)
Input Frequency Range
Loop Bandwidth
Phase Margin
ANALOG PLL2 (APLL_2)
VCO Frequency Range
Phase Frequency Detector (PFD)
Input Frequency Range
Loop Bandwidth
Phase Margin
ANALOG PLL3 (APLL_3)
VCO Frequency Range
Phase Frequency Detector (PFD)
Input Frequency Range
Loop Bandwidth
Phase Margin
Min Typ
2424
320
240
68
3232
320
240
68
4842
320
240
68
4040
320
240
68
Max
3132
350
3905
350
5650
350
4748
350
Unit Test Conditions/Comments
MHz
MHz
kHz
Degrees
The AD9554-1 evaluation software finds the optimal value
for this setting based on user’s input.
MHz
MHz
kHz
Degrees
The AD9554-1 evaluation software finds the optimal value
for this setting based on user’s input.
MHz
MHz
kHz
Degrees
The AD9554-1 evaluation software finds the optimal value
for this setting based on user’s input.
MHz
MHz
kHz
Degrees
The AD9554-1 evaluation software finds the optimal value
for this setting based on user’s input.
Rev. B | Page 11 of 99
11 Page | ||
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