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PDF PMS308416B Data sheet ( Hoja de datos )
| Número de pieza | PMS308416B | |
| Descripción | 256Mb (16Mb x 16) SDRAM | |
| Fabricantes | PM Tech | |
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πPM Tech
Document Title
256Mb (16Mb x 16) SDRAM Datasheet
Revision History
Revision
0.1
Date
March, 2010
Page
―
Original
PMS308416B
Notes
This document is a general product description and subject to change without notice.
1 page  
πPM Tech
Block Diagram
PMS308416B
4M x 16
4M x 16
4M x 16
4M x 16
Rev 0.1
5 March 2010
5 Page 
πPM Tech
PMS308416B
Auto Refresh Command
(/CS, /RAS, /CAS = LOW, /WE, CKE = HIGH)
This command executes the Auto Refresh operation. The row address and bank to be refreshed are
automatically generated during this operation. All banks must be placed in the idle state before executing
this command. The stipulated period (tRC) is required for a single refresh operation, and no other commands
can be executed during this period. The SDRAM goes to the idle state after the internal refresh operation
completes. This command must be executed at least 8192 times every 64ms. This command corresponds to
CBR Auto Refresh in conventional DRAMs.
Self Refresh Command
(/CS, /RAS, /CAS, CKE = LOW, /WE = HIGH)
This command executes the Self Refresh operation. The row address, the bank, and the refresh interval to
be refreshed are automatically generated internally during this operation. The Self Refresh operation is
started by dropping the CKE pin from HIGH to LOW. The Self Refresh operation continues as long as the
CKE pin remains LOW and there is no need for external control of any other pins. The Self Refresh
operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed
until the SDRAM internal recovery period (tRC) has elapsed. After the Self Refresh, since it is impossible to
determine the address of the last row to be refreshed, an Auto Refresh should immediately be performed for
all addresses (8,192 cycles).
Burst Stop Command
(/CS, /WE = LOW, /RAS, /CAS = HIGH)
This command forcibly terminates burst read and write operations. When this command is executed during a
burst read operation, data output stops after the /CAS latency period has elapsed.
No Operation
(/CS = LOW, /RAS, /CAS, /WE = HIGH)
This command has no effect on the SDRAM.
Device Deselect Command
(/CS = HIGH)
This command does not select the SDRAM for an object of operation. In other words, it performs no
operation with respect to the SDRAM.
Power Down Command
(CKE = LOW)
When both banks are in the idle state, or when at least one of the banks is not in the idle state, this
command can be used to suppress device power dissipation by reducing device internal operations to the
absolute minimum. Power Down mode is started by dropping the CKE pin from HIGH to LOW. Power Down
mode continues as long as the CKE pin is held LOW. All pins other than CEK pins are invalid and none of
the other commands can be executed in this mode. The Power Down operation is terminated by raising the
CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (tCKA) has
elapsed. Since this command differs from the Self Refresh command described above in that the refresh
operation is not performed automatically internally, the refresh operation must be performed within the
refresh period (tREF). Thus the maximum time that Power Down mode can be held is just under the refresh
cycle time.
Rev 0.1
11 March 2010
11 Page | ||
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