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PDF AT91C140 Data sheet ( Hoja de datos )
| Número de pieza | AT91C140 | |
| Descripción | Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
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Features
• ARM7TDMI® ARM® Thumb® Processor Core
– In-Circuit Emulator, 36 MHz Operation
• Ethernet Bridge
– Dual Ethernet 10/100 Mbps MAC Interface
– 16-Kbyte Frame Buffer
• 1 K-Byte Boot ROM, Embedding a Boot Program
– Enable Application Download from DataFlash®
• External Bus Interface
– On-chip 16-bit SDRAM Controller
– 4-Chip Select Static Memory Controller
• Multi-level Priority, Individually Maskable, Vectored Interrupt Controller
• Three 16-bit Timer/Counters
• Two UARTs with Modem Control Lines
• Serial Peripheral Interface (SPI)
• Two PIO Controllers, Managing up to 48 General-purpose I/O Pins
• Available in a 208-lead PQFP Package
• Power Supplies
– VDDIO 3.3V nominal
– VDDCORE and VDDOSC 1.8V nominal
• -40°C to + 85°C Operating Temperature Range
AT91 ARM®
Thumb®
Microcontrollers
AT91C140
1. Description
The AT91C140 is a member of the Atmel AT91 16- and 32-bit microcontroller family
based on the ARM7TDMI processor core. This processor has a high performance
32-bit RISC architecture with a high density 16-bit instruction set and very low power
consumption.
In addition, the AT91C140 integrates a double Ethernet 10/100 base-T MAC capable
of operating as an Ethernet bridge, thus making it ideally suited for networking appli-
cations. It supports a wide range of memory devices such as SDRAM, SRAM and
Flash and embeds an extensive array of peripherals.
The device is manufactured using Atmel’s high-density CMOS technology. By com-
bining the ARM7TDMI processor core with an expansive assortment of peripheral
functions and low-power oscillators and PLL on a monolithic chip, the Atmel
AT91C140 is a powerful microcontroller that provides a highly flexible and cost effec-
tive solution to many networking applications.
6069C–ATARM–15-Sep-05
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AT91C140
4. Peripheral Multiplexing on PIO Lines
The AT91C140 features two PIO Controllers, PIOA and PIOB, multiplexing I/O lines of the
peripheral set.
The PIO Controller A manages 15 I/O lines, PA0 to PA12, PA19 and PA22.
The PIO Controller B manages only 10 I/O lines, PB0 to PB9.
Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O. Multiplexing of the
PIO Controller A is given in Table 4-1 on page 6. Multiplexing of the PIO Controller B is given
in Table 4-2 on page 6.
6069C–ATARM–15-Sep-05
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AT91C140
8. System Controller
The AT91C140 features a System Controller that takes care of and controls:
• the Test Mode
• the Reset
• the System Clocks
• the Chip Identifier
The System Controller manages the reset of all the system and integrates a clock generator,
made up of an oscillator and a PLL.
8.1 Test
The AT91C140 features a test pin (TST). This pin must be tied low for normal operations.
Using the AT91C140 with the TST pin at a high level might lead to unpredictable results.
8.2 Reset Controller
8.2.1 NRST Pin
The AT91C140 is reset by asserting the NRST pin low. It should be asserted for a time ade-
quate to ensure the startup of the oscillator on a power on, and at least 1 ACLK cycle for a
warm reset. As the ACLK switches on the 31,25kHz (assuming the crystal is at 16 MHz) as
soon as the reset is asserted, it must remain low for at least 32 µs. The first instruction fetch
happens 10 ACLK cycles after the reset releases.
8.2.2
System Reset
A reset initializes the user interface registers to their default states as defined in the peripheral
sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from
address zero. Except for the program counter and the Current Program Status Register, the
ARM processor registers do not have defined reset states. When NRST is active, the inputs of
the AT91C140 must be held at valid logic levels to reduce the power consumption to a
minimum.
8.2.3
Boot Memory and Remap Command
When NRST is released, the PA0 pin is sampled to determine if the ARM processor should
boot from internal ROM or from external memory connected to NCE0. The details of the boot
operations are described in ”Memory Controller (MC)” on page 16. The Boot Program is
described in ”Boot Program” on page 24.
After a reset, the RM bit in the Mode Register reflects the state of the PA0 pin. Then, writing
this bit at 1 removes the ROM from the address 0. Writing it at 0 remaps the ROM at address
0x0.
8.3 Clock Generator
The AT91C140 features a Clock Generator based on a 16 MHz oscillator and a PLL. It pro-
vides all the clocks of the system, including a clock signal named ACLK, to the ARM
processor, to the memory controller and to the External Bus Interface and to all the embedded
peripherals
The ACLK signal is also provided on the ACLKO pin, through PIO Controller A.
Figure 8-1 below shows the architecture of the Clock Generator.
6069C–ATARM–15-Sep-05
11
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| PDF Descargar | [ Datasheet AT91C140.PDF ] | |
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