PDF ICS87973I-147 Data sheet ( Hoja de datos )

Número de pieza	ICS87973I-147
Descripción	1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fabricantes	IDT
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No Preview Available ! LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ ZERO DELAY BUFFER ICS87973I-147 General Description ICS HiPerClockS™ The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The ICS87973I-147 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. The input frequency range is 6MHz to 120MHz. The ICS87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1.System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2.Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3.Zero Delay buffer for Synchronous memory: Fanout up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. Features • Fully integrated PLL • Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync • Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 10MHz to 150MHz • VCO range: 240MHz to 500MHz • Output skew: 200ps (maximum) • Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum) • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Compatible with PowerPC™and Pentium™Microprocessors • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment 39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL 40 41 42 43 44 45 46 47 48 49 50 51 52 1 26 25 24 23 22 21 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 1 ICS87973I-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View ICS87973DYI-147 REV. A DECEMBER 9, 2008 1 page ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Table 2. Pin Characteristics Symbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions VDD, VDDA, VDDO = 3.465V Minimum 5 Typical 4 51 7 Maximum 18 12 Units pF kΩ pF Ω Function Tables Table 3A. Output Bank Configuration Select Function Table Inputs Outputs Inputs FSEL_A1 FSEL_A0 QA FSEL_B1 FSEL_B0 0 0 ÷4 0 0 0 1 ÷6 0 1 1 0 ÷8 1 0 1 1 ÷12 1 1 Outputs QB ÷4 ÷6 ÷8 ÷10 Inputs FSEL_C1 FSEL_C0 00 01 10 11 Outputs QC ÷2 ÷4 ÷6 ÷8 Table 3B. Feedback Configuration Select Function Table Inputs Outputs FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 000 ÷4 001 ÷6 010 ÷8 011 ÷10 100 ÷8 101 ÷12 110 ÷16 111 ÷20 Table 3C. Control Input Select Function Table Control Pin Logic 0 VCO_SEL VCO/2 REF_SEL CLK0 or CLK1 CLK_SEL CLK0 PLL_SEL BYPASS PLL nMR/OE Master Reset/Output High-Impedance INV_CLK Non-Inverted QC2, QC3 Logic 1 VCO XTAL CLK1 Enable PLL Enable Outputs Inverted QC2, QC3 IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 5 ICS87973DYI-147 REV. A DECEMBER 9, 2008 5 Page ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS87973I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω VDDA .01µF 10µF Figure 2. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_BIAS = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_BIAS in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_BIAS should be 1.25V and R2/R1 = 0.609. Single Ended Clock Input V_Bias C1 0.1u VDD R1 1K CLK nCLK R2 1K Figure 3. Single-Ended Signal Driving Differential Input IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 11 ICS87973DYI-147 REV. A DECEMBER 9, 2008 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ICS87973I-147	1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER	ICS
ICS87973I-147	1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER	IDT

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