|
|
PDF BU64987GWZ Data sheet ( Hoja de datos )
| Número de pieza | BU64987GWZ | |
| Descripción | Bi-directional VCM driver | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de BU64987GWZ (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
Bi-directional VCM driver for Auto focus
BU64987GWZ
General Description
The BU64987GWZ is designed to drive Bi-directional
voice coil motors. Additionally the driver is able to source
the output current without the need for a direction control
signal. The drivers include ISRC (intelligent slew rate
control) to reduce mechanical ringing to optimize the
camera’s autofocus capabilities.
Features
1.8V Power Supply
Bi-directional Constant Current Driver
Current Source and Sink Output
10 bit Resolution Current Control
2-wire Serial Interface (I2C Fm+ compatible)
Integrated Current Sense Resistor
Power-on Reset
Thermal Shutdown Protection
Applications
Mobile Camera Module
Bi-directional VCM Actuators
Key Specifications
Power Supply Range:
Standby Current:
Internal Resistance:
Master Clock:
Maximum Output Current:
Temperature Range:
1.6V to 1.98V
0µA (Typ)
1.3Ω (Typ)
400kHz (Typ)
+100mA, -100mA (Typ)
-25°C to +85°C
Packages
UCSP30L1A
W (Typ) x D (Typ) x H (Max)
0.77mm x 1.2mm x 0.33mm
Typical Application Circuit
1.8V
1.8V
VDVDCC
00.1.1toto
1100µuFF
I2C
master
Power save
VREF
TSD
SCL Direction
LOGIC
10 bit
DAC
Control
&
SDA Pre driver
OUTPUT
Control_A
OUTPUT
Control_B
POR
Current
+
Sense
-
GND
Isource
VCM MTR
Isink
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
.www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
○This product is not designed protection against radioactive rays
1/21
TSZ02201-0K1H0B601870-1-2
6. Oct.2016 Rev.001
1 page  
BU64987GWZ
Power-up/Power-down Sequence and Function Timing Diagrams
①②③
VVCDCD
SSCCLL
T_reset
④
T_off
PPSS 0
1
0
EENN
InItneternrnaall_EENN
0
T_EN
0
1
T_EN
10
1
0
0
TaTragreget tD_DAACC
RReeffeerreennccee_DDAACC
0x200
0x80
TTaargrgete_tDDACA1C
1
RReeffeerreennccee_DDACA1C' 1
( Ex. 0x300 )
TaTargrgeett_DDAACC2 2
RReeffeerreenncec_eDDACA1C 1
( Ex. 0xC0 )
0x200
0x80
Figure 4. Timing Diagram
The following commands are shown in Figure , the timing diagram:
1=Power save release, 2=Target DAC code change #1, 3=Reference DAC code change, 4=Target DAC code change #2
Table 1. Power Sequence Timing Delays
Parameter
Time from VDD going high until first 2-wire
Serial Interface command
Time delay for rush current protection
Time delay of last 2-wire Serial Interface
command until VDD going low
Symbol
T_reset
T_EN
T_off
Min
Limit
Typ
Max
Unit
20 -
- µs
47.5 50 52.5 µs
1.3 -
- µs
2-wire Serial BUS Format
Write mode（R/W = 0)
Output from Master
Output from Slave
Update
S 0 0 0 1 1 0 0 R/W A PS EN W2 W1 W0 M D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
Read mode
S 0 0 0 1 1 0 0 0 A PS EN W2 W1 W0 M ※ ※ A
Write
Update W (register address)
S 0 0 0 1 1 0 0 1 A PS EN W2 W1 W0 M CD9 CD8 A CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 A
S : start signal
A : acknowledge
Read
P : stop signal
nA : non acknowledge
※ : Don`t care
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/21
TSZ02201-0K1K0B601860-1-2
6. Oct.2016 Rev.001
5 Page 
BU64987GWZ
Controlling Step Mode
Step mode is the control period in which the lens is moved by small output current steps. During step mode it is possible
to control the step resolution and step time in order to generate just enough output current to float the lens with minimal
ringing effects. Ringing can be better controlled by choosing a large value for the step time and a small value for the
step resolution with the trade off of a greater settling time. The step time and step resolution should be chosen depending
on the acceptable system limits of ringing vs. settling time.
Step mode is used when M=1, the reference DAC set to 0, and the present DAC code is in between point A and point B.
Typically this mode is only used during ISRC operation between point A and B, however it is possible to move the lens to
point C using only step mode if point C is set such that point C is only 1 DAC code greater than point B.
Step mode is controlled by the 5-bit step time, stt[4:0], and 3-bit step resolution, str[2:0], values stored in register W[2:0]
= 0b111. The step time is set by the 5 LSBs and the step resolution is set by the 3 MSBs of the third byte write while
using register W[2:0] = 0b111.
Table 5. Step Time Settings
stt[4:0] Step Time stt[4:0] Step Time stt[4:0] Step Time stt[4:0] Step Time
0b00000
-
0b01000
400 µs
0b10000
800 µs
0b11000
1200 µs
0b00001
50 µs
0b01001
450 µs
0b10001
850 µs
0b11001
1250 µs
0b00010
100 µs
0b01010
500 µs
0b10010
900 µs
0b11010
1300 µs
0b00011
150 µs
0b01011
550 µs
0b10011
950 µs
0b11011
1350 µs
0b00100
200 µs
0b01100
600 µs
0b10100
1000 µs
0b11100
1400 µs
0b00101
250 µs
0b01101
650 µs
0b10101
1050 µs
0b11101
1450 µs
0b00110
300 µs
0b01110
700 µs
0b10110
1100 µs
0b11110
1500 µs
0b00111
350 µs
0b01111
750 µs
0b10111
1150 µs
0b11111
1550 µs
Table 6. Step Resolution Settings
str[2:0]
Step
Resolution
str[2:0]
0b000
0b001
-
1 LSB
0b010
0b011
Step
Resolution
2 LSB
3 LSB
str[2:0]
0b100
0b101
Step
Resolution
4 LSB
5 LSB
str[2:0]
0b110
0b111
Step
Resolution
6 LSB
7 LSB
The BU64987GWZ has an absolute output current range of 120mA which corresponds to a step resolution of
0.117mA/LSB.
Using a normal VCM actuator (non-bidirectional), it is possible to skip step mode during ISRC operation if a simpler
autofocus code sequence is desired. If there is no issue with moving the lens to point B using direct mode, then the
DAC code for point A should be left equal to 0. Additionally if the point A register is not set after the driver is initialized,
then the driver will automatically move the lens to point B with direct mode since the default value for point A is 0.
Controlling ISRC Mode
ISRC mode is the control period in which the lens is already floating and the driver smoothly moves the lens based on
the proprietary behavior of the ISRC algorithm. ISRC operation keeps ringing at a minimum while achieving the fastest
possible settling time based on the ISRC operational conditions.
ISRC mode is used when M=1, the reference DAC set to 0, and the present DAC code is greater than the DAC code for
point B. ISRC mode is also used when M=1 and the reference DAC set to a non-zero value. If the target DAC code
for point C is set so that the value is too large and will cause excess ringing, the point C DAC code is automatically
updated with a driver pre-determined value to minimize the ringing effect. When M=1 and the reference DAC set to 0,
the driver will automatically switch between direct mode, step mode, and ISRC mode when the point A, B, and C DAC
code conditions are met. The condition for this automatic transitioning to occur is when the register values for point B
and point C are set to values other than 0 and then the sequence will start when the EN bit is set equal to 1. Please
note that updates to point B and C DAC codes should be avoided during a focus operation in order to minimize poor
ringing effects.
DAC code
C
B
ISRC DAC codes*
A
Step mode
Direct mode
0
Start sequence
ISRC mode ※ ISRC DAC codes
– the details of ISRC
operation are
proprietary
Time (ms)
Figure 12. Three Mode Sequential Operation (Shown as DAC Codes) for Traditional VCM Actuators
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/21
TSZ02201-0K1K0B601860-1-2
6. Oct.2016 Rev.001
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet BU64987GWZ.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| BU64987GWZ | Bi-directional VCM driver | ROHM Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |