PDF MC141627 Data sheet ( Hoja de datos )

Número de pieza	MC141627
Descripción	Advanced PAL Comb Filter-II
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC141627/D Product Preview Advanced PAL Comb Filter-II (APCF-II) The Advanced PAL Comb Filter–II is a video signal processor for VCRs, LDPs, and TVs. It separates the Luminance Y and Chrominance C signal from the NTSC/PAL composite signal by using digital signal processing techniques which minimize dot–crawl and cross–color. The built–in 4xFSC PLL circuit allows a subcarrier signal input, which generates 4xFSC clock for video signal processing. This filter allows a video signal input of an extended frequency bandwidth by using a 4xFSC clock. The built–in vertical enhancer circuit reduces noise and dot crawl on the Luminance Y signal. The built–in A/D and D/A converters allow easy connection to analog video circuits. • Built–In High Speed 8–Bit A/D Converter • Four Line Memories (4540 Bytes) • Advanced Comb–II Process • Built–In Vertical Enhancer • Vertical Dot Reduction Process • Two Built–In High Speed 8–Bit D/A Converters • Built–In 4xFSC PLL Circuit • Built–In Clamp Circuit • Digital Interface Mode • On–Chip Reference Voltage for A/D Converter MC141627 FT SUFFIX QFP PACKAGE CASE 898 48 1 ORDERING INFORMATION MC141627FT Quad Flat Package (QFP) PIN ASSIGNMENT D3 D2 D1 D0 BYPASS VH GND(D) VCC(D) FSC N/M PAL/NTSC Comb/BPF 36 37 48 1 25 24 TE1 TE0 MODE1 MODE0 CLK(AD) GND(D) NC CLC CLout Vin RBT 13 RTP 12 NC = NO CONNECTION This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0.1 8/96 M©OMTotOoroRlaO, InLcA. 1996 MC141627 1 1 page ADC – DAC GENERAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic Symbol Voltage Gain Output Bandwidth (at – 3 dB at PAL) Differential Gain DG Differential Phase DP Bias Current (at Ibias = 10 kΩ) Ibias CLAMP CIRCUIT CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic Clamp Mode Output Voltage* * Output of CLout when connecting Vin – CLout. BK/VH CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic Bypass Switching Time, at Normal Mode VH Switching Time, at Normal Mode Comb/BPF Switching Time, at Normal Mode Symbol Vclys Symbol Min — 6.4 — — — Min — Min — — — VERTICAL ENHANCER LEVEL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic Symbol Noise Slice Level, at Normal Mode White Enhance Level, at Normal Mode Black Enhance Level, at Normal Mode Min 0 0 0 GENERAL SIGNAL DELAY (VCC = 5.0 V, TA = 25°C ± 3°C) Characteristic PAL B/G/H/I Mode (2299.5 Clock) NTSC Mode (939.5 Clock) PAL N Mode (1867.5 Clock) PAL M Mode (1851.5 Clock) Symbol Min — — — — Typ – 4.4 7.3 — — 135 Typ 0.6 Typ 9 4 16 Typ 6 10 11 Typ 129.66 65.62 130.34 129.45 Max Unit — dB — MHz 5% 5 Deg — µA Max Unit —V Max Unit — Clock — Clock — Clock Max Unit 15 Bits 15 Bits 15 Bits Max Unit — µs — µs — µs — µs CLOCK INPUT DATA (D0 – D7) tds tdh tr tf Figure 1. Digital Signal Input Timing Diagram (During Digital Input Comb Filter Mode) Clamp Circuit Characteristics (VCC = 5.0 V, TA = 25°C ± 3°C) Clamp Mode Output Voltage, Vcly (Non–input when connecting Vin – CLout) Vcly = (VTP – VBT) (N + 1) / 256 + VBT ± 50 mV where N = Clamp Code Input (N < 255) • If the calculated value of the output voltage, Vcly > Vclys, then Vcly = Vclys • Clamp Value N is fixed, N = 4. MOTOROLA MC141627 5 5 Page EMI SUPPRESSION When using ICs in or near television receiver circuits, EMI (electromagnetic interference) and subsequent unwanted display artifacts and distortion are probable unless adequate EMI suppression is implemented. A common misconception is that some offending digital device is the culprit. This is er- roneous in that an IC itself has insufficient surface area to produce sufficient radiation. The device, while it is the gener- ator of interfering signals, must be coupled to an antenna be- fore EMI is radiated. The source for the EMI is not the IC which generates the offending signals but rather the circuitry which is attached to the IC. Potential EMI signals are generated by all digital devices. Whether they become a nuisance is dependent upon their frequency and whether they have a sufficient antenna. The frequency and number of these signals is affected by both circuit design within the IC and the manufacturing process. Device speed is also a major contributor of potential EMI. Be- cause the design is determined by the anticipated applica- tion, the manufacturing process is fixed and the drive for speed ever increasing, the only effective point to implement EMI suppression is in the PC board design. The PC board usually is the antenna which radiates the EMI. The most effi- cient method of minimizing EMI radiation is to minimize the efficiency of this antenna. The most common cause of inadequate EMI suppression lies with the ground system of the suspected digital devices. As pointed out previously, di/dt transitions can be significant in digital circuits. If the di/dt transitions appear in the ground system and the ground system is inductive, the harmonics present in these transitions are a source of potential EMI sig- nals. The unfortunate result of putting digital devices on a reactive ground system is guaranteed EMI problems. The area which should be addressed first as a potential EMI source is the ground. Without an adequate ground sys- tem, EMI cannot be effectively reduced by decoupling. If at all possible, the ground should be a complete unbroken plane. Figure 5 shows two examples of relieving ground around device pins. When relieving vias and plated through holes, large areas of ground loss should be avoided. When the relief pattern is equal to half the distance between pins, over etching and process errors may remove ground be- tween pins. If sufficient ground around enough pins are re- moved, the ground system can become isolated or nearly isolated “patches” which will appear inductive. If ground, such as the vicinity of an IC, must be removed, replace with a cross hatch of ground lines with the mesh as small as pos- sible. If a single unbroken plane can be devoted to the ground system, EMI can usually be sufficiently suppressed by using ferrite beads on suspect EMI paths and decoupling with ade- quate values of capacitors. The value of the decoupling capacitor depends on the frequency and amplitude of the offending signals. Ferrite beads are available in a wide vari- ety of shape, size and material to fit virtually any application. Choose a ferrite bead for desired impedance at the de- sired frequency and construct a low pass filter using one or more appropriate capacitors in a “L”, “T” or “PI” arrangement. Use only capacitors of low inductive and resistive properties such as ceramic or mica. Install filters in series with each IC pin suspected of contributing offending EMI signals and as close to the pin as possible. Analysis using a spectrum ana- lyzer can help determine which pins are suspect. Where PC board costs constrain the number of layers available, and if the EMI frequencies are far removed from the frequencies of operation, ferrite beads and decoupling capacitors may still be effective in reducing EMI emissions. Where only two (or in some cases, only one!) layer is used, the ground system is always reactive and poses an EMI problem. If the offending EMI and normal operating frequen- cy differ sufficiently, filtering can still work. An “island” is constructed in the ground system for the digi- tal device using ferrite beads and decoupling capacitors as shown by the example in Figure 6. The ground must be cut so that the digital ground for the device is isolated from the rest of the ground system. Next choose a ferrite bead of the appropriate value. Install this bead between the isolated ground and the ground system. Install low pass filters in all suspect lines with the capacitor closest to the device pin con- nected to the isolated ground in all signal lines where EMI is suspect. Also cut the power to the device and insert a ferrite bead as shown in Figure 6. Finally, decouple the device be- tween the power pin(s) and isolated ground pin(s) using a low inductive/resistive capacitor of adequate value. The methods described above will work acceptably when the EMI frequency and the frequency of operation of the de- vice generating the EMI differ greatly. Where the EMI is dis- turbing the high VHF or UHF channels and the device generating the EMI is operating within the NTSC/PAL band- width, the energy contained in the harmonics generating the EMI is situated well above the operating frequency and suppressing this type of EMI poses no great problem. How- ever, if the EMI is present on low VHF channels and/or the operation of the device is outside the NTSC/PAL bandwidth, such as a 2X pixel clock or 4xFSC oscillator, compromise be- tween video quality and suppression complexity is usually re- quired to obtain an acceptable solution. For those cases where the operating frequency of the device is very near the frequency of the EMI disturbance, careful attention to PCB layout, multiple layer PCB and even shielding may be neces- sary to obtain an acceptable design. MOTOROLA MC141627 11 11 Page

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