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PDF MCP39F511 Data sheet ( Hoja de datos )
| Número de pieza | MCP39F511 | |
| Descripción | Power-Monitoring IC | |
| Fabricantes | Microchip | |
| Logotipo |  |
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MCP39F511
Power-Monitoring IC with Calculation and Energy Accumulation
Features
• Power Monitoring Accuracy Capable of 0.1%
Error Across 4000:1 Dynamic Range
• Built-In Calculations on Fast 16-Bit Processing
Core
- Active, Reactive, Apparent Power
- True RMS Current, RMS Voltage
- Line Frequency, Power Factor
• 64-bit Wide Import and Export Active Energy
Accumulation Registers
• 64-bit Four Quadrant Reactive Energy
Accumulation Registers
• Signed Active and Reactive Power Outputs
• Dedicated Zero Crossing Detection (ZCD) Pin
Output with Less than 200 µs Latency
• Dedicated PWM Output Pin with Programmable
Frequency and Duty Cycle
• Automatic Event Pin Control through Fast Voltage
Surge Detection Less than 5 ms Delay
• Two Wire Serial Protocol with Selectable Baud
Rate Up to 115.2 kbps using Universal
Asynchronous Receiver/Transmitter (UART)
• Four Independent Registers for Minimum and
Maximum Output Quantity Tracking
• Fast Calibration Routines and Simplified
Command Protocol
• 512 Bytes User-Accessible EEPROM through
Page Read/Write Commands
• Low-Drift Internal Voltage Reference, 10 ppm/°C
Typical
• 28-lead 5x5 QFN Package
• Extended Temperature Range -40°C to +125°C
Applications
• Power Monitoring for Home Automation
• Industrial Lighting Power Monitoring
• Real-Time Measurement of Input Power for
AC/DC Supplies
• Intelligent Power Distribution Units
Description
The MCP39F511 is a highly integrated, complete
single-phase power-monitoring IC designed for
real-time measurement of input power for
AC/DC power supplies, power distribution units,
consumer and industrial applications. It includes
dual-channel Delta-Sigma ADCs, a 16-bit calculation
engine, EEPROM and a flexible 2-wire interface. An
integrated low-drift voltage reference with 10 ppm/°C in
addition to 94.5 dB of SINAD performance on each
measurement channel allows for better than 0.1%
accurate designs across a 4000:1 dynamic range.
Package Types
MCP39F511
5x5 QFN*
28 27 26 25 24 23 22
EVENT1 1
21 AGND
NC 2
20 AN_IN
NC 3
UART_RX 4
COMMONA 5
19 V1+
EP
29
18 V1-
17 I1-
OSCI 6
16 I1+
OSCO 7
15 EVENT2
8 9 10 11 12 13 14
*Includes Exposed Thermal Pad (EP);
see Table 3-1.
2015 Microchip Technology Inc.
DS20005393B-page 1
1 page  
MCP39F511
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C,
MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Calibration, Calculation and Event Detection Times
Auto-Calibration Time
tCAL
— 2N x (1/fLINE)
Minimum Time
for Voltage Surge/Sag
tAC_SASU
— see
Section 7.0
Detection
—
—
ms Note 3
ms Note 4
24-Bit Delta-Sigma ADC Performance
Analog Input
Absolute Voltage
VIN -1 — +1 V
Analog Input
Leakage Current
AIN — 1 — nA
Differential Input
Voltage Range
Offset Error
Offset Error Drift
(I1+ – I1-), -600/GAIN — +600/GAIN mV VREF = 1.2V,
(V1+ – V1-)
proportional to VREF
VOS
-1
— +1 mV
— 0.5 — µV/°C
Gain Error
GE -4 — +4 % Note 5
Gain Error Drift
— 1 — ppm/°C
Differential Input
Impedance
ZIN 232 —
142 —
— k G = 1
— k G = 2
72 — — k G = 4
38 — — k G = 8
36 — — k G = 16
33 — — k G = 32
Signal-to-Noise
and Distortion Ratio
SINAD
92
94.5
— dB Note 6
Total Harmonic Distortion
THD
—
-106.5
-103
dBc Note 6
Signal-to-Noise Ratio
SNR
92
95
— dB Note 6
Spurious Free
Dynamic Range
SFDR
—
111
— dB Note 6
Crosstalk
CTALK
—
-122
— dB
AC Power
AC PSRR
—
-73
— dB AVDD and
Supply Rejection Ratio
DVDD = 3.3V + 0.6VPP,
100 Hz, 120 Hz, 1 kHz
DC Power
DC PSRR
—
-73
— dB AVDD and DVDD = 3.0 to
Supply Rejection Ratio
3.6V
Note 1:
2:
3:
Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4
line cycles.
Specification by design and characterization; not production tested.
N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for
50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance
Curves” for typical performance.
6: VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the
performance listed in the respective specification.
8: Lower baud rates selectable only on system versions 0xFA14 and later.
2015 Microchip Technology Inc.
DS20005393B-page 5
5 Page 
MCP39F511
3.0 PIN DESCRIPTION
The description of the pins are listed in Table 3-1.
TABLE 3-1:
MCP39F511
5x5 QFN
1
2, 3, 8, 9
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24, 27
25
26
28
29
PIN FUNCTION TABLE
Symbol
Function
EVENT1
NC
UART_RX
COMMONA
OSCI
OSCO
RESET
AVDD
UART_TX
COMMONB
PWM
EVENT2
I1+
I1-
V1-
V1+
AN_IN
AGND
ZCD
REFIN+/OUT
DGND
DVDD
MCLR
DR
EP
Event 1 Output pin
No Connect (must be left floating)
UART Communication RX pin
Common pin A, to be connected to pin 13 (COMMONB)
Oscillator Crystal Connection pin or External Clock Input pin
Oscillator Crystal Connection pin
Reset pin for Delta-Sigma ADCs
Analog Power Supply pin
UART Communication TX pin
Common pin B, to be connected to pin 5 (COMMONA)
Pulse-Width Modulation (PWM) Output pin
Event 2 Output pin
Noninverting Current Channel Input for 24-bit ADC
Inverting Current Channel Input for 24-bit ADC
Inverting Voltage Channel Input for 24-bit ADC
Noninverting Voltage Channel Input for 24-bit ADC
Analog Input for SAR ADC
Analog Ground Pin, return path for internal analog circuitry
Zero Crossing Detection Output
Noninverting Voltage Reference Input and Internal Reference Output Pin
Digital Ground pin, return path for internal digital circuitry
Digital Power Supply pin
Master Clear for device
Data Ready (must be left floating)
Exposed Thermal Pad (to be connected to pins 24 and 27 (DGND))
2015 Microchip Technology Inc.
DS20005393B-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet MCP39F511.PDF ] | |
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