PDF MX812 Data sheet ( Hoja de datos )

Número de pieza	MX812
Descripción	VSR CODEC
Fabricantes	MX-COM
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No Preview Available ! DATABULLETIN M X 8 1 2 VSR CODEC WITH DRAM CONTROL PRELIMINARY INFORMATION Features and Applications • Half-Duplex Voice Storage and Retrieval • Serial Bus µProcessor Control • On-Chip DRAM Controller • Up To 2 Minutes of High-Quality Recorded Audio • Answering Functions and Voice- Notepad • Low-Power 5-Volt CMOS • Selectable Sample Rates and “Memory Size” MX812DW 28-pin SOIC MX812J 28-pin CDIP CLOCK AUDIO OUT VBIAS AUDIO IN EBIAS VDD VSS CHIP SELECT SERIAL CLOCK COMMAND DATA REPLY DATA IRQ CLOCK GENERATOR DEMOD CVSD CODEC MOD DRAM CONTROL POWER METER STATUS REGISTER SERIAL C-BUS INTERFACE and LOGIC STORE/PLAY/WAIT COMMAND BUFFER MODE REGISTER Figure 1 - MX812 Voice Store and Retrieve Codec WE CAS RAS1 A10/R2 A9 A8 EXTERNAL A7 DRAM A6 A5 1 or 2 x A4 1Mbit A3 DRAM Chips A2 A1 or A0 1 x D 4Mbit DRAM Chip DGND © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. 1 page VSR CODEC with DRAM CONTROL Application Information ...... + 5.0V 5 MX812 PRELIMINARY INFORMATION + 5.0V VDD WE CAS RAS1 A10/R2 A9 A8 A7 MX812 A6 A5 A4 A3 A2 A1 A0 DGND D VCC W CAS RAS A10 A9 A8 A7 4Mbit. A6 DRAM A5 A4 A3 A2 A1 A0 Q D VSS VDD WE CAS RAS1 A10/R2 A9 A8 A7 MX812 A6 A5 A4 A3 A2 A1 A0 DGND D VCC W CAS RAS A9 A8 A7 1Mbit. A6 DRAM. A5 No.1 A4 A3 A2 A1 A0 Q D VSS VCC W CAS RAS A9 A8 A7 1Mbit. A6 DRAM. A5 No.2 A4 A3 A2 A1 A0 Q D VSS Figure 4 - Example DRAM Connections Choice of DRAM Devices DRAM devices chosen should be standard 1,048,576 x 1 or 4,194,304 x 1 Dynamic Random Access memories, with ‘CAS before RAS’ refresh, and a Row Address access time of 200 nano-seconds or less. BANK A SELECT INPUTS B 'HC04 'HC00 WE CAS RAS1 A10/R2 A9 A8 A7 MX812 A6 A5 A4 A3 A2 A1 A0 D W CAS RAS A10 A9 A8 A7 A6 4Mbit A5 DRAM A4 No. 1 A3 A2 A1 A0 Q D W CAS RAS A10 A9 A8 A7 A6 4Mbit A5 DRAM A4 No. 2 A3 A2 A1 A0 Q D Figure 5 - Use of External Elements to Drive Two 4-MBit DRAM Chips Driving Two 4-MBit DRAM Sections By adding external logic circuitry, the MX812 can be configured to drive two 4-MBit DRAM sections. This will have the effect of doubling the available storage time. i.e. 4 minutes at 32kbps. With reference to the circuitry shown in Figure 5: With the Mode Register MS Bit set to “0” the MX812 treats the DRAM sections as two 1-Mbit devices. The external logic makes each 4-MBit DRAM appear as four 1-MBit banks selected by the Bank Select lines ‘A’ and ‘B.’ Bank Select Inputs AB 00 10 01 11 DRAM No 1 Pages 0 – 1023 DRAM No 2 Pages 1024 – 2047 © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. 5 Page VSR CODEC with DRAM CONTROL 11 MX812 PRELIMINARY INFORMATION Specifications Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not suggested. Supply Voltage Input Voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25°C Derating Operating Temperature Storage Temperature -0.3 to 7.0 V -0.3 to (VDD+0.3V) ±30mA ±20mA 800mW Max. 10mW/°C -40°C to +85°C -55°C to +125°C Operating Limits All devices were measured under the following conditions unless otherwise noted. VDD = 5.0V TAMB = 25°C Xtal/Clock f = 4.00MHz 0 Audio Level 0dB ref = 308mVrms @ 1kHz Reply Data Line loaded with 50pF/200kΩ to VSS Characteristics Static Values Supply Voltage Supply Current Enabled Powersaved Analog Input Impedance Analog Output Impedance (Decode) Analog Output Impedance (Encode or Powersave) See Note 1 1 Min. 4.5 – – – – – Typ. 5.0 3.0 1.0 100 1.0 500 Max. 5.5 – – – – – Unit V mA mA kΩ kΩ kΩ DRAM Interface Input Logic “1” Input Logic “0” Output Logic “1” (at Io = -120µA) Output Logic “0” (at Io = 120µA) Input Leakage Current (at VIN = 0 to VDD) Input Capacitance 2 2 3 3 4 2 3.5 – – – – 1.5 2.7 – – – – 0.4 -1.0 – 1.0 – 10.0 – V V V V µA pF Digital Interface Input Logic “1” Input Logic “0” IIN (logic “1” or “0”) Output Logic Levels Output Logic “1” (-120µA) Output Logic “0” (360µA) I Out Tri-state (logic “1” or “0”) Input Capacitance IOX (VOut = 5V) 5 5 5 6 7 6 5 8 3.5 – –– -1.0 – 4.6 – –– -4.0 – –– –– –V 1.5 V 1.0 µA –V 0.4 V 4.0 µA 7.5 pF 4.0 µA © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. 11 Page

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