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PDF AOZ1110 Data sheet ( Hoja de datos )
| Número de pieza | AOZ1110 | |
| Descripción | 4A Synchronous EZBuck Regulator | |
| Fabricantes | Alpha & Omega Semiconductors | |
| Logotipo |  |
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AOZ1110
4A Synchronous EZBuck Regulator
Not Recommended For New Designs
General Description
The AOZ1110QI is a high efficiency, easy to use, 4A
synchronous buck regulator optimized for portable
electronic devices. The AOZ1110QI works from a 2.7V to
5.5V input voltage range, and provides up to 4A of
continuous output current with an output voltage
adjustable down to 0.8V. With a 1% output accuracy
rating, the AOZ1110 is designed for low tolerance
applications, such as DSPs and FPGAs.
The AOZ1110QI is available in a 24-pin 4X4 QFN
package and is rated over a -40°C to +85°C ambient
temperature range.
Features
z 2.7V to 5.5V input voltage range
z 30mΩ high-side and 20mΩ low-side MOSFET
z Efficiency up to 95%
z Adjustable soft start
z Output voltage adjustable down to 0.8V
z 4A continuous output current
z Selectable 500kHz & 1MHz PWM operation
z Cycle-by-cycle current limit
z Over-voltage protection
z Short-circuit protection
z Thermal shutdown
z Power good indicator
z Small size 4x4 QFN-24 package
Applications
z Point of load DC/DC conversion for DSPs, FPGAs,
ASICs and microprocessors
z DVD and HDD
z Notebook PCs
z Telecom/Networking/Datacom equipment
Typical Application
VIN
C1
22µF
Ceramic
RC
CC
Rev. 1.0 October 2010
5V
R3 MCU
VDD VIN PGOOD
EN
FSEL
AOZ1110QI LX
COMP
SS
Css = NC
AGND
PGND
FB
L1 1.0uH
R1
R2
Figure 1. Typical Application
www.aosmd.com
VOUT
C2, C3
22µF
Ceramic
Page 1 of 16
1 page  
AOZ1110
Electrical Characteristics (Continued)
TA = 25°C, VIN = VEN = 3.3V, unless otherwise specified(3)
Symbol
Parameter
PWM OUTPUT STAGE
RDS(ON)
High-Side PFET On-Resistance
High-Side PFET Leakage
RDS(ON)
Low-Side NFET On-Resistance
Low-Side NFET Leakage
POWER GOOD
VOLPG
PG LOW Voltage
PG Leakage Current
PG Upper Threshold Voltage
PG Lower Threshold Voltage
PG Hysteresis Voltage
tPG PG Falling Edge Deglitch Time
Condition
VIN = 5V
VEN = 0V, VLX = 0V
VLX = 5V
VEN = 0V
I(sink) = 1.0mA
V = 5.5V
Fraction of set point
Fraction of set point
Min.
110
80
Typ.
33
19
115
85
3
120
Max.
64
10
30
10
0.3
±1
120
90
Notes:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
4. Guaranteed by design.
Units
mΩ
μA
mΩ
μA
V
μA
%
%
%
μs
Rev. 1.0 October 2010
www.aosmd.com
Page 5 of 16
5 Page 
AOZ1110
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
-----------------------1-------------------------
2π × CO × ESRCO
where;
CO is the output filter capacitor,
RL is load resistor value,
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1110QI. For most
cases, a series capacitor and resistor network connected
to the COMP pin sets the pole-zero and is adequate for a
stable high-bandwidth control loop.
In the AOZ1110QI, FB pin and COMP pin are the
inverting input and the output of internal error amplifier. A
series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
fp2
=
----------------G-----E----A-----------------
2π × CC × GVEA
where;
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V,
and, CC is the compensation capacitor in Figure1.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
fZ2
=
-----------------1------------------
2π × CC × RC
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
strategy for choosing Rc and Cc is to set the cross over
frequency with Rc and set the compensator zero with CC.
Using selected crossover frequency, fC, to calculate RC:
RC
=
fC
×
--V----O----
VFB
×
-----2---π-----×-----C-----O------
GEA × GCS
where;
fC is desired crossover frequency. For best performance, fC is
set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V;
GCS is the current sense circuit transconductance, which is
10 A/V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected cross-
over frequency. CC can is selected by:
CC
=
--------------1---.--5---------------
2π × RC × fp1
The equation above can also be simplified to:
CC
=
C-----O-----×-----R-----L-
RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Rev. 1.0 October 2010
www.aosmd.com
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AOZ1110.PDF ] | |
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