PDF IDT8T49N445I Data sheet ( Hoja de datos )

Número de pieza	IDT8T49N445I
Descripción	QUAD Universal Frequency Translator
Fabricantes	Integrated Device Technology
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No Preview Available ! FemtoClock® NG QUAD Universal Frequency Translator IDT8T49N445I DATA SHEET General Description The IDT8T49N445I is a quad PLL with FemtoClock® NG technology. The IDT8T49N445I integrates low phase noise Frequency Translation / Synthesizer and jitter attenuation. It includes alarm and monitoring functions suitable for networking and communications applications. The device has four fully independent PLLs, each PLL is able to generate any output frequency in the 0.98MHz - 312.5MHz range and most output frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for details). A wide range of input reference clocks may be used as the source for the output frequency. Each PLL of IDT8T49N445I has three operating modes to support a very broad spectrum of applications: 1) Frequency Synthesizer • Synthesizes output frequencies from an external reference clock REFCLK. • Fractional feedback division is used, so there are no requirements for any specific input reference clock frequency to produce the desired output frequency with a high degree of accuracy. 2) High-Bandwidth Frequency Translator • Applications: PCI Express, Computing, General Purpose • Translates any input clock in the 16MHz - 710MHz frequency range into any supported output frequency. • This mode has a high PLL loop bandwidth in order to track input reference changes, such as Spread-Spectrum Clock modulation. 3) Low-Bandwidth Frequency Translator • Applications: Networking & Communications. • Translates any input clock in the 8kHz -710MHz frequency range into any supported output frequency. • This mode supports PLL loop bandwidths in the 10Hz - 580Hz range and makes use of an external reference clock REFCLK to provide significant jitter attenuation. Each PLL provides factory-programmed default power-up configuration burned into One-Time Programmable (OTP) memory. The configuration is specified by the customer and are programmed by IDT during the final test phase from an on-hand stock of blank devices. To implement other configurations, these power-up default settings can be overwritten after power-up using the I2C interface and the device can be completely reconfigured. Features • Fourth generation FemtoClock® NG technology • Four fully independent PLLs • Universal Frequency Translator™ Frequency Synthesizer and Jitter attenuator • Output is programmable as LVPECL or LVDS • Programmable output frequency: 0.98MHz up to 1,300MHz • Differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL • Input frequency range: 8kHz - 710MHz (Low-Bandwidth mode) • Input frequency range: 16kHz - 710MHz (High-Bandwidth mode) • REFCLK frequency range: 16MHz - 40MHz • Input clock monitor on each PLL will smoothly switch between redundant input references • Operation reference frequency range: 16MHz - 40MHz • Input clock monitor and alarm • Factory-set register configuration for power-up default state • Power-up default configuration • Configuration customized via One-Time Programmable ROM • Settings may be overwritten after power-up via I2C • I2C Serial interface for register programming • RMS phase jitter at 161.1328125MHz, using 40MHz REFCLK (12kHz - 20MHz): 465fs (typical), Low Bandwidth Mode (FracN) • RMS phase jitter at 400MHz, using 40MHz REFCLK (12kHz - 20MHz): 333fs (typical), synthesizer Mode (integer FB) • Full 2.5V supply mode • -40°C to 85°C ambient operating temperature • 10mm X 10mm CABGA • Lead-free (RoHS 6) packaging IDT8T49N445AASGI REVISION A JUNE 28, 2013 1 ©2013 Integrated Device Technology, Inc. 1 page IDT8T49N445I Data Sheet Pin Assignment FEMTOCLOCK® NG QUAD UNIVERSAL FREQUENCY TRANSLATOR J QD GND VCCO_D nc LF1C LF0C GND nQC QC H nQD GND CLKD nCLKD LOCKD nc RSVD GND GND G GND RSVD nc nc SCLK SDATA nc CLKC VCCO_C F LF0D nc VCC_D nc VCC_C nc nc nCLKC nC E LFID LOCKA VCCA_D RSVD REFCLK nc VCCA_C LOCKC LF1B D nc nCLKA nc nc VCCO_B nc VCC_B nc LF0B C VCCA_A CLKA nc VCCO_A LOCKB nc nc RSVD GND B QA GND GND nc VCC_A nCLKB CLKB GND nQB A nQA GND LF0A LF1A nc VCCA_B GND QB 1 2 3 45 6 7 8 9 IDT8T49N445I Pin Map 80-Ball Lead 10mm x 10mm x1mm package body CABGA Package (bottom view) IDT8T49N445AASGI REVISION A JUNE 28, 2013 5 ©2013 Integrated Device Technology, Inc. 5 Page IDT8T49N445I Data Sheet FEMTOCLOCK® NG QUAD UNIVERSAL FREQUENCY TRANSLATOR Table 4G. BWx[6:0] Bits Mode BWx[6] BWx[5] BWx[4] BWx[3] Synthesizer Mode PLL2_LFx[1] PLL2_LFx[0] DSM_ORDx DSM_ENx High-Bandwidt h Mode PLL2_LFx[1] PLL2_LFx[0] DSM_ORDx DSM_ENx Low-Bandwidth Mode ADC_GAINx[3] ADC_GAINx[2] ADC_GAINx[1] ADC_GAINx[0] BWx[2] PLL2_CPx[1] PLL2_CPx[1] PLL1_CPx[1] BWx[1] PLL2_CPx[0] PLL2_CPx[0] PLL1_CPx[0] BWx[0] PLL2_LOW_L CPx PLL2_LOW_L CPx PLL2_LOW_L CPpx Table 4H. Functions of Fields in BW[6:0] Register Bits Function PLL2_LFx[1:0] Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes for PLLx. Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4I for settings. DSM_ORDx Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation. DSM_ENx Enables Delta-Sigma Modulator for PLLx. 0 = Disabled - feedback in integer mode only 1 = Enabled - feedback in fractional mode PLL2_CPx[1:0] Upper loop PLL charge pump current settings for PLLx: 00 = 173A (defaults to this setting in Low Bandwidth Mode) 01 = 346A 10 = 692A 11 = reserved PLL2_LOW_LCPx Reduces Charge Pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register settings or high VCO operating frequency (>2.4GHz) for PLLx. ADC_GAINx[3:0] Gain setting for ADC in Low Bandwidth Mode for PLLx. PLL1_CPx[1:0] Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode) for PLLx: 00 = 800A 01 = 400A 10 = 200A 11 = 100A Table 4I. Upper Loop (PLL2) Bandwidth Settings Desired Bandwidth PLL2_CP PLL2_LOW_ICP PLL2_LF Frequency Synthesizer Mode 200kHz 00 1 00 400kHz 01 1 01 800kHz 10 1 10 2MHz 10 1 11 High Bandwidth Frequency Translator Mode 200kHz 00 1 00 400kHz 01 1 01 800kHz 10 1 10 4MHz 10 0 11 NOTE: To achieve 4MHz bandwidth, reference to the phase detector should be 80MHz. IDT8T49N445AASGI REVISION A JUNE 28, 2013 11 ©2013 Integrated Device Technology, Inc. 11 Page

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Número de pieza	Descripción	Fabricantes
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