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PDF MR44V064A Data sheet ( Hoja de datos )
| Número de pieza | MR44V064A | |
| Descripción | FeRAM | |
| Fabricantes | LAPIS | |
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MR44V064A
64k(8,192-Word 8-Bit) FeRAM (Ferroelectric Random Access Memory)
FEDR44V064A-01
Issue Date: Apr. 22, 2013
GENERAL DESCRIPTION
The MR44V064A is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. The MR44V064A is accessed using Two-wire
Serial Interface ( I2C BUS ).Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup
required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks,
such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and
the power consumption during a write can be reduced significantly.
The MR44V064A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 8,192-word 8-bit configuration I2C BUS Interface
• A single 3.3 V typ (2.5V to 3.6V) power supply
• Operating frequency:
3.4MHz(Max) HS-mode
• Read/write tolerance
400KHz(Max) F/S-mode
1012 cycles/bit
• Data retention
10 years
• Guaranteed operating temperature range
40 to 85C (Extended temperature version)
• Package options:
8-pin plastic SOP (P-SOP8-200-1.27-T2K)
1/16
1 page  
FEDR44V064A-01
MR44V064A
COMMAND
BYTE WRITE CYCLE
Arbitrary data is written to FeRAM. When to write only 1 byte, byte write is normally used.
start condition
slave address with LSB is 0 (write)
1st and 2nd word address
byte of write data.
stop condition
S
T
A
R
T
Slave address
W
R
I
T
E
1 0 1 0 A2 A1 A0
1st WORD address
W
000A
12
W
A
8
2nd WORD address
WW
AA
70
D
7
AAA
CCC
KKK
Write data
S
T
O
P
D
0
A
C
K
PAGE WRITE CYCLE
When to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. By page
write cycle, up to 8,192 bytes data can be written. When data of the maximum bytes or higher is sent, data from
the first byte is overwritten.
S
T
A
R
T
Slave address
W
R
I
T
E
1 0 1 0 A2 A1 A0
1st WORD address
W
000A
12
W
A
8
2nd WORD address
WW
AA
70
D
7
AAA
CCC
KKK
Write data
DD
07
A
C
K
Write data
S
T
O
P
D
0
A
C
K
CURRENT ADDRESS READ CYCLE
Current read cycle is a command to read data of internal address register without designating address, and is used
when to verify just after write cycle.
S
T
A
R
T
Slave address
R
E
A
D
1 0 1 0 A2 A1 A0
D7
A
C
K
Read data
S
T
O
P
D0
N
A
C
K
5/16
5 Page 
TIMING
SCL
tR
SDA
(input)
tR
SDA
(output)
tF
tSU:DAT
tBUF
1/fSCL
tF tHIGH
tSP
tLOW
tHD:DAT
tAA tDH
FEDR44V064A-01
MR44V064A
tSP
SCL
SDA
(input)
tSU:STA
tHD:STA
START BIT
tSU:STO
STOP BIT
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MR44V064A.PDF ] | |
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