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PDF MC100H641 Data sheet ( Hoja de datos )
| Número de pieza | MC100H641 | |
| Descripción | SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC100H641 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Single Supply PECL-TTL
1:9 Clock Distribution Chip
MC10H641
MC100H641
The MC10H/100H641 is a single supply, low skew translating 1:9 clock
driver. Devices in the Motorola H600 translator series utilize the 28–lead
PLCC for optimal power pinning, signal flow through and electrical
performance.
The device features a 24mA TTL output stage, with AC performance
specified into a 50pF load capacitance. A latch is provided on–chip. When
LEN is LOW (or left open, in which case it is pulled LOW by the internal
pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces
all outputs LOW. Both the LEN and EN pins are positive ECL inputs.
The VBB output is provided in case the user wants to drive the device
with a single–ended input. For single–ended use the VBB should be
connected to the D input and bypassed with a 0.01µF capacitor.
The 10H version of the H641 is compatible with positive MECL 10H™
logic levels. The 100H version is compatible with positive 100K levels.
• PECL–TTL Version of Popular ECLinPS E111
• Low Skew
• Guaranteed Skew Spec
• Latched Input
• Differential ECL Internal Design
• VBB Output for Single–Ended Use
• Single +5V Supply
• Logic Enable
• Extra Power and Ground Supplies
• Separate ECL and TTL Supply Pins
SINGLE SUPPLY
PECL–TTL 1:9 CLOCK
DISTRIBUTION CHIP
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
Pinout: 28–Lead PLCC (Top View)
GT Q6 VT Q7 VT Q8 GT
25 24 23 22 21 20 19
GT 26
18 VBB
Q5 27
17 D
VT 28
16 D
Q4 1
VT 2
15 VE
14 LEN
Q3 3
13 GE
GT 4
12 EN
5 6 7 8 9 10 11
GT Q2 VT Q1 VT Q0 GT
MECL 10H is a trademark of Motorola, Inc.
11/93
© Motorola, Inc. 1996
2–1
PIN NAMES
Pins
GT, VT
GE, VE
D, D
VBB
Q0–Q8
EN
LEN
Function
TTL GND, TTL VCC
ECL GND, ECL VCC
Signal Input (Positive ECL)
VBB Reference Output
(Positive ECL)
Signal Outputs (TTL)
Enable Input (Positive ECL)
Latch Enable Input
(Positive ECL)
REV 3
1 page  
MC10H641 MC100H641
VCC Dependence
TTL and CMOS devices show a significant propagation
delay dependence with VCC. Therefore the VCC variation in a
system will have a direct impact on the total skew of the clock
distribution network. When calculating the skew between two
devices on a single board it is very likely an assumption of
identical VCC’s can be made. In this case the number provided
in the data sheet for part–to–part skew would be overly
conservative. By using Figure 4 the skew given in the data
sheet can be reduced to represent a smaller or zero variation
in VCC. The delay variation due to the specified VCC variation
is ≈270ps. Therefore, the 1ns window on the data sheet can
be reduced by 270ps if the devices in question will always
experience the same VCC. The distribution of the propagation
delay ranges given in the data sheet is actually a composite
of three distributions whose means are separated by the fixed
difference in propagation delay at the typical, minimum and
maximum VCC.
140
100
60
20
–20
–60 TPHL
TPLH
–100
–140
4.75 4.85 4.95 5.05 5.15
VCC (V)
Figure 4. ∆TPD versus VCC
5.25
Capacitive Load Dependence
As with VCC the propagation delay of a TTL output is
intimately tied to variation in the load capacitance. The skew
specifications given in the data sheet, of course, assume
equal loading on all of the outputs. However situations could
arise where this is an impossibility and it may be necessary to
estimate the skew added by asymmetric loading. In addition
the propagation delay numbers are provided only for 50pF
loads, thus necessitating a method of determining the
propagation delay for alternative loads.
Figure 5 shows the relationship between the two
propagation delays with respect to the capacitive load on the
output. Utilizing this graph and the 50pF limits the specification
of the H641 can be mapped into a spec for either a different
value load or asymmetric loads.
1.15
1.10
1.05 TPLH
1.00
0.95 MEASURED
0.90
TPHL
0.85
0.80 THEORETICAL
0.75
0
10 20 30 40 50 60 70 80
CAPACITIVE LOAD (pF)
Figure 5. TPD versus Load
90 100
Rise/Fall Skew Determination
The rise–to–fall skew is defined as simply the difference
between the TPLH and the TPHL propagation delays. This
skew for the H641 is dependent on the VCC applied to the
device. Notice from Figure 4 the opposite relationship of TPD
versus VCC between TPLH and TPHL. Because of this the
rise–to–fall skew will vary depending on VCC. Since in all
likelihood it will be impossible to establish the exact value for
VCC, the expected variation range for VCC should be used. If
this variation will be the ±5% shown in the data sheet the
rise–to–fall skew could be established by simply subtracting
the fastest TPLH from the slowest TPHL; this exercise yields
1.41ns. If a tighter VCC range can be realized Figure 4 can be
used to establish the rise–to–fall skew.
Specification Limit Determination Example
The situation pictured in Figure 6 will be analyzed as an
example. The central clock is distributed to two different cards;
on one card a single H641 is used to distribute the clock while
on the second card two H641’s are required to supply the
needed clocks. The data sheet as well as the graphical
information of this section will be used to calculate the skew
between H641a and H641b as well as the skew between all
three of the devices. Only the TPLH will be analyzed, the TPHL
numbers can be found using the same technique. The
following assumptions will be used:
– All outputs will be loaded with 50pF
– All outputs will toggle at 30MHz
– The VCC variation between the two boards is ±3%
– The temperature variation between the three
devices is ±15°C around an ambient of 45°C.
– 500LFPM air flow
The first task is to calculate the junction temperature for the
devices under these conditions. Using the power equation
yields:
PD = ICC (no load) * VCC +
VCC * VS * f * CL * # outputs
= 1.8 * 48mA * 5V + 5V * 3V * 30MHz *
50pF * 9
= 432mW + 203mW = 635mW
MECL Data
DL122 — Rev 6
2–5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC100H641.PDF ] | |
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