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PDF MC10E445 Data sheet ( Hoja de datos )
| Número de pieza | MC10E445 | |
| Descripción | 4-BIT SERIAL / PARALLEL CONVERTER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC10E445 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4ĆBit Serial/Parallel Converter
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both
4-bit conversion and a two chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q0, the second to
Q1 etc.
MC10E445
MC100E445
• On-Chip Clock ÷4 and ÷8
• 2.0Gb/s Data Rate Capability
• Differential Clock and Serial Inputs
• VBB Output for Single-Ended Input Applications
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• Internal 75kΩ Input Pulldown Resistors
• Extended 100E VEE Range of –4.2V to –5.46V
4-BIT SERIAL/
PARALLEL CONVERTER
Two selectable serial inputs provide a loopback capability for testing
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn–1. For each additional
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to “swallow”
a clock pulse, effectively shifting a bit from the Qn to the Qn–1 output (see
Timing Diagram B).
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will
function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle
thus allowing for an 8-bit conversion scheme using two E445’s. When cascaded in an 8-bit conversion scheme the devices will
not operate at the 2.0Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on
cascading the E445.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a 0.01µF capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB
can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPS™ data book.
Upon power-up the internal flip-flops will attain a random state. To synchronize multiple E445’s in a system the master reset
must be asserted.
PIN NAMES
Pin
SINA, SINA
SINB, SINB
SEL
Q0–Q3
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNCH
Function
Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Selector Pin
Parallel Data Outputs
Differential Clock Inputs
Differential ÷4 Clock Output
Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input
FUNCTION TABLES
Mode
Conversion
L 4-Bit
H 8-Bit
SEL
H
L
Serial Input
A
B
SINA SINA
MODE NC VCCO
25 24 23 22 21 20 19
SINB 26
18
SINB 27
17
SEL 28
16
VEE
1 Figure 1. 28–Lead Pinout 15
(Top View)
CLK 2
14
CLK 3
13
VBB 4
12
5 6 7 8 9 10 11
CL/8 CL/8 VCCO CL/4 CL/4 VCCO Q3
SOUT
SOUT
VCC
Q0
Q1
VCCO
Q2
8/97
© Motorola, Inc. 1997
1
REV 3
1 page  
APPLICATIONS INFORMATION
MC10E445 MC100E445
The MC10E/100E445 is an integrated 1:4 serial to parallel
converter. The chip is designed to work with the E446 device
to provide both transmission and receiving of a high speed
serial data path. The E445, can convert up to a 2.0Gb/s NRZ
data stream into 4-bit parallel data. The device also provides
a divide by four clock output to be used to synchronize the
parallel data with the rest of the system.
The E445 features multiplexed dual serial inputs to
provide test loop capability when used in conjunction with the
E446. Figure 4 illustrates the loop test architecture. The
architecture allows for the electrical testing of the link without
requiring actual transmission over the serial data path
medium. The SINA serial input of the E445 has an extra
buffer delay and thus should be used as the loop back serial
input.
PARALLEL
DATA
SOUT
SOUT
TO SERIAL
MEDIUM
PARALLEL
DATA
SINA
SINA
SINB
SINB
FROM
SERIAL
MEDIUM
increased. The delay between the two clocks can be
increased until the minimum delay of clock to serial out would
potentially cause a serial bit to be swallowed (Figure 6).
CLOCK
CLOCK
SERIAL
INPUT
DATA
E445a
SIN SOUT
SIN SOUT
Q3 Q2 Q1 Q0
E445b
SIN
SIN
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
PARALLEL OUTPUT DATA
Q3 Q2 Q1 Q0
CLOCK
Tpd CLK
to SOUT
800ps
1150ps
100ps
Figure 4. Loopback Test Architecture
Figure 5. Cascaded 1:8 Converter Architecture
The E445 features a differential serial output and a divide
by 8 clock output to facilitate the cascading of two devices to
build a 1:8 demultiplexer. Figure 5 illustrates the architecture
for a 1:8 demultiplexer using two E445’s; the timing diagram
for this configuration can be found on the following page.
Notice the serial outputs (SOUT) of the lower order converter
feed the serial inputs of the the higher order device. This feed
through of the serial inputs bounds the upper end of the
frequency of operation. The clock to serial output
propagation delay plus the setup time of the serial input pins
must fit into a single clock period for the cascade architecture
to function properly. Using the worst case values for these
two parameters from the data sheet, TPD CLK to SOUT =
1150ps and tS for SIN = –100ps, yields a minimum period of
1050ps or a clock frequency of 950MHz.
The clock frequency is significantly lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E445. By
delaying the clock feeding the second E445 relative to the
clock of the first E445 the frequency of operation can be
With a minimum delay of 800ps on this output the clock for
the lower order E445 cannot be delayed more than 800ps
relative to the clock of the first E445 without potentially
missing a bit of information. Because the setup time on the
serial input pin is negative coincident excursions on the data
and clock inputs of the E445 will result in correct operation.
CLOCK A
CLOCK B
Tpd CLK
to SOUT
800ps
1150ps
Figure 6. Cascade Frequency Limitation
ECLinPS and ECLinPS Lite
DL140 — Rev 4
5
MOTOROLA
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