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PDF MC10E211 Data sheet ( Hoja de datos )
| Número de pieza | MC10E211 | |
| Descripción | 1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:6 Differential Clock
Distribution Chip
The MC10E/100E211 is a low skew 1:6 fanout device designed
explicitly for low skew clock distribution applications. The device can be
driven by either a differential or single-ended ECL or, if positive power
supplies are used, PECL input signal (PECL is an acronym for Positive
ECL, PECL levels are ECL levels referenced to +5V rather than ground).
If a single-ended input is to be used the VBB pin should be connected to
the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB
supply is designed to act as the switching reference for the input of the
E211 under single-ended input conditions, as a result this pin can only
source/sink up to 0.5mA of current.
MC10E211
MC100E211
1:6 DIFFERENTIAL
CLOCK DISTRIBUTION CHIP
• Guaranteed Low Skew Specification
• Synchronous Enabling/Disabling
• Multiplexed Clock Inputs
• VBB Output for Single-Ended Use
• Internal 75kΩ Input Pulldown Resistors
• Common and Individual Enable/Disable Control
• High Bandwidth Output Transistors
• Extended 100E VEE Range of –4.2V to –5.46V
The E211 features a multiplexed clock input to allow for the distribution
of a lower speed scan or test clock along with the high speed system
clock. When LOW (or left open in which case it will be pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock input.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next
negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be
enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the
disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all
associated specifications are referenced to the negative edge of the CLK input.
The output transitions of the E211 are faster than the standard ECLinPS™ edge rates. This feature provides a means of
distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits
guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the
recommended termination schemes please refer to the applications information section of this data sheet.
FUNCTION TABLE
CLK
SCLK
SEL
H/L X
X H/L
Z* Z*
L
H
X
* Z = Negative transition of CLK or SCLK
ENx
L
L
H
Q
CLK
SCLK
L
ECLinPS is a trademark of Motorola Inc.
5/95
© Motorola, Inc. 1996
2–1
REV 3
1 page  
MC10E211 MC100E211
APPLICATIONS INFORMATION
Differential versus Single-Ended Use
As can be seen from the data sheet, to minimize the skew
of the E211 the device must be used in the differential mode.
In the single-ended mode the propagation delays are
dependent on the relative position of the VBB switching
reference. Any VBB offset from the center of the input swing
will add delay to either the TPLH or TPHL and subtract delay
from the other. This increase and decrease in delay will lead
to an increase in the duty cycle skew and thus part-to-part
skew. The within-device skew will be independent of the VBB
and therefore will be the same regardless of whether the
device is driven differentially or single-endedly.
For applications where part-to-part skew or duty cycle
skew are not important the advantages of single-ended clock
distribution may lead to its use. Using single-ended
interconnect will reduce the number of signal traces to be
routed, but remember that all of the complimentary outputs
still need to be terminated therefore there will be no reduction
in the termination components required. To use the E211 with
a single-ended input the arrangement pictured in Figure 2b
should be used. If the input to the differential CLK inputs are
AC coupled as pictured in Figure 2a the dependence on a
centered VBB reference is removed. The situation pictured
will ensure that the input is centered around the bias set by
the VBB. As a result when AC coupled the AC specification
limits for a differential input can be used. For more
information on AC coupling please refer to the interfacing
section of the design guide in the ECLinPS data book.
pulse. On initial power up the enable flip flops will randomly
attain a stable state, therefore precautions should be taken
on initial power up to ensure the E211 is in the desired state.
IN
0.001µF
IN
50Ω
0.01µF
VBB
Figure 2a. AC Coupled Input
IN
IN
Using the Enable Pins
Both the common enable (CEN) and the individual
enables (ENx) are synchronous to the CLK or SCLK input
depending on which is selected. The active low signals are
clocked into the enable flip flops on the negative edges of the
E211 clock inputs. In this way the devices will only be
disabled when the outputs are already in the LOW state. The
internal propagation delays are such that the delay to the
output through the distribution buffers is less than that
through the enable flip flops. This will ensure that the
disabling of the device will not slice any time off the clock
0.01µF
VBB
Figure 2b. Single-Ended Input
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–5
MOTOROLA
5 Page | ||
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| PDF Descargar | [ Datasheet MC10E211.PDF ] | |
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