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PDF MC100E210 Data sheet ( Hoja de datos )

Número de pieza MC100E210
Descripción Differential Fanout Buffer
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No Preview Available ! MC100E210 Hoja de datos, Descripción, Manual

MC100E210
5V ECL Dual 1:4, 1:5
Differential Fanout Buffer
The MC100E210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device
features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The
device features fully differential clock paths to minimize both device and
system skew. The dual buffer allows for the fanout of two signals through
a single chip, thus reducing the skew between the two fundamental
signals from a parttopart skew down to an outputtooutput skew. This
capability reduces the skew by a factor of 4 as compared to using two
LVE111’s to accomplish the same task.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 1020 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 1020 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
For more information on using PECL, designers should refer to
Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
Features
Dual Differential Fanout Buffers
200 ps ParttoPart Skew
50 ps Typical OutputtoOutput Skew
Low Voltage ECL/PECL Compatible
The 100 Series Contains Temperature Compensation
28lead PLCC Packaging
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = 4.2 V to 5.7 V
Internal Input 75 KW Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
ESD Protection: Human Body Model; >2 KV,
Machine Model; >200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 179 devices
These are PbFree Devices
http://onsemi.com
MARKING
DIAGRAM
1 28
PLCC28
FN SUFFIX
CASE 776
MC100E210FNG
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100E210FNG
PLCC28 37 Units / Rail
(PbFree)
MC100E210FNR2G PLCC28 500 Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 3
1
Publication Order Number:
MC100E210/D

1 page




MC100E210 pdf
MC100E210
PACKAGE DIMENSIONS
PLCC28
FN SUFFIX
CASE 77602
ISSUE F
NY BRK
D
B 0.007 (0.180) M T L-M S N S
U 0.007 (0.180) M T L-M S N S
Z
L− −M
WD
28 1 V
X
VIEW DD
G1 0.010 (0.250) S T L-M S N S
A 0.007 (0.180) M T L-M S N S
Z
R 0.007 (0.180) M T L-M S N S
CE
0.004 (0.100)
G J TSEATING
PLANE
G1 VIEW S
0.010 (0.250) S T L-M S N S
H 0.007 (0.180) M T L-M S N S
K1
K
F
VIEW S
0.007 (0.180) M T L-M S N S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.021 0.33 0.53
G 0.050 BSC
1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 --- 0.51 ---
K 0.025 --- 0.64 ---
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y --- 0.020 --- 0.50
Z 2 _ 10_ 2 _ 10_
G1 0.410 0.430 10.42 10.92
K1 0.040 --- 1.02 ---
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