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PDF MC100LVEL91 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL91 | |
| Descripción | Triple PECL to ECL Translator | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple PECL to ECL Translator
The MC100LVEL/EL91 is a triple PECL to ECL translator. The
MC100LVEL91 receives low voltage PECL signals and translates them to
differential ECL output signals. The MC100EL91 receives standard
voltage PECL signals and translates them to differential ECL output
signals.
• MC100LVEL91 Supports Low Voltage Operation
• MC100LVEL91 Has 620ps Typical Propagation Delays
• MC100EL91 Supports Standard Voltage Operation
• MC100EL91 Has 670ps Typical Propagation Delays
• Fully Differential Design
• 20–lead SOIC Packaging
A VBB output is provided for interfacing with single ended PECL signals
at the input. If a single ended input is to be used the VBB output should be
connected to the D input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the switching reference
for the EL/LVEL91 under single ended input switching conditions, as a
result this pin can only source/sink up to 0.5mA of current.
To accomplish the level translation the EL/LVEL91 requires three
power rails. The VCC supply should be connected to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins are connected to the system ground plain. Both VEE and VCC
should be bypassed to ground via 0.01µF capacitors.
Under open input conditions, the D input will be biased at VCC/2 and
the D input will be pulled to GND. This condition will force the Q output to
a low, ensuring stability.
MC100LVEL91
MC100EL91
DW SUFFIX
20–LEAD PLASTIC SOIC WIDE PACKAGE
CASE 751D–04
PIN NAMES
Pins
Function
Dn
Qn
PECL_VBB
PECL/LVPECL Inputs
ECL/LVECL Outputs
PECL Reference Voltage Output
VCC Q0
20 19
Q0 GND Q1
18 17 16
Q1 GND Q2
15 14 13
Q2 VCC
12 11
ECL ECL ECL
PECL
PECL
PECL
1 2 3 4 5 6 7 8 9 10
VCC D0 D0
D1 D1
D2 D2 VEE
Figure 1. 20–Lead Pinout (Top View) and Logic Diagram
8/97
© Motorola, Inc. 1997
4–1
REV 1
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| PDF Descargar | [ Datasheet MC100LVEL91.PDF ] | |
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| MC100LVEL91 | Triple PECL to ECL Translator | Motorola Semiconductors |
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