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PDF IRU3018 Data sheet ( Hoja de datos )
| Número de pieza | IRU3018 | |
| Descripción | 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Data Sheet No. PD94144
IRU3018
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC,
LDO CONTROLLER AND 200mA ON-BOARD LDO REGULATOR
FEATURES
Provides single chip solution for Vcore, GTL+ & clock
supply
200mA On-Board LDO Regulator
Designed to meet the latest Intel specification for
Pentium II™
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear regulator controller on board for 1.5V GTL+
supply
Loss-less Short Circuit Protection with HICCUP
Synchronous operation allows maximum efficiency
patented architecture allows fixed frequency opera-
tion as well as 100% duty cycle during dynamic
load
Soft-Start
High current totem pole driver for direct driving of the
external power MOSFET
Power Good Function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher output and generates a fault signal
Thermal Shutdown
Logic Level Enable Input
APPLICATIONS
Total Power Solution for Pentium II processor
application
DESCRIPTION
The IRU3018 controller IC is specifically designed to meet
Intel specification for Pentium II™ microprocessor appli-
cations as well as the next generation of P6 family pro-
cessors. The IRU3018 provides a single chip controller
IC for the Vcore, LDO controller for GTL+ and an internal
200mA regulator for clock supply which are required for
the Pentium II applications. These devices feature a pat-
ented topology that in combination with a few external
components as shown in the typical application circuit,
will provide in excess of 18A of output current for an on-
board DC-DC converter while automatically providing the
right output voltage via the 5-bit internal DAC. The
IRU3018 also features loss-less current sensing for both
switchers by using the RDS(ON) of the high-side power
MOSFET as the sensing resistor, internal current limit-
ing for the clock supply, and a Power Good window com-
parator that switches its open collector output low when
any one of the outputs is outside of a pre-programmed
window. Other features of the device are: Under-voltage
lockout for both 5V and 12V supplies, an external pro-
grammable soft-start function, programming the oscilla-
tor frequency via an external resistor, Over-Voltage Pro-
tection (OVP) circuitry for both switcher outputs and an
internal thermal shutdown.
TYPICAL APPLICATION
5V
Note: Pentium II is trademark of Intel Corp
3.3V
VOUT3
IRU3018
SWITCHER1
CONTROL
LINEAR
CONTROL
LINEAR
REGULATOR
VOUT1
VOUT2
Figure 1 - Typical application of IRU3018.
PACKAGE ORDER INFORMATION
TA (8C)
0 To 70
DEVICE
PACKAGE
IRU3018CW 24-Pin Plastic SOIC WB
Rev. 1.6
07/16/02
www.irf.com
1
1 page  
IRU3018
PIN#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN SYMBOL
Fault / Rt
Fb2
VIN2
VOUT2
Gnd
Gate3
Fb3
En
Fb1
VSEN1
OCSet1
PGnd
LGate1
Phase1
UGate1
PIN DESCRIPTION
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if the
switcher output exceeds the OVP trip point, the Fault pin switches to 12V and the soft-
start cap is discharged. If the Fault pin is to be connected to any external circuitry, it
needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator which its output is VOUT4.
This pin is the input that provides power for the internal LDO regulator. It is also monitored
for the under-voltage and over-voltage conditions.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator which its output drive is Gate3.
This pin is a TTL compatible Enable pin. When this pin is left open or pulled high, the
device is enabled and when it is pulled low, it will disable the switcher and the LDO
controller (VOUT3) leaving the internal 200mA regulator operational. When signal is given to
enable the device, both switcher and VOUT3 will go through soft-start, the same as during
start-up.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to VOUT1 and Gnd to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from VOUT1 to Fb1 must be less than 100V.
This pin is internally connected to the under-voltage and over-voltage comparators sens-
ing the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the CS threshold depending on the RDS of the power MOSFET. An external capaci-
tor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor (typi-
cally 1mF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high side power MOSFET for the Core supply.
Rev. 1.6
07/16/02
www.irf.com
5
5 Page 
IRU3018
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two set of output conditions that this regula-
tor must meet for Vcore:
a) Vo=2.8V, Io=14.2A, DVo=185mV, DIo=14.2A
b) Vo=2V, Io=14.2A, DVo=140mV, DIo=14.2A
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total DVo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
ESR
[
100
14.2
=
7mV
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500mF, 6.3V has an ESR of less than 36mV typical.
Selecting 6 of these capacitors in parallel has an ESR
of ≈ 6mV which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
Gnd pin of the IRU3018 is 5mV and if the total DI, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level shift-
ing during the load transient eases the requirement for
the output capacitor ESR at the cost of load regulation.
One can show that the new ESR requirement eases up
by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without volt-
age level shifting must be 7mV then after level shifting
the new ESR will only need to be 8.5mV if the trace
resistance is 5mV (7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
Rs [ 23(Vspec - 0.023Vo - DVo) / DI
Where:
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage spec
Vo = Output voltage
DVo = Output ripple voltage
DI = load current step
For example, assuming:
Vspec = ±140mV = ±0.1V for 2V output
Vo = 2V
DVo = assume 10mV = 0.01V
DI = 14.2A
Then the Rs is calculated to be:
Rs [ 23(0.140 - 0.0232 - 0.01) / 14.2 = 12.6mV
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6mV, the power dissipated is:
Io23Rs = 14.22312.6 = 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5mV, then the power dissipated is about 1W
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7mV which translated to ≈ 6
of the 1500mF, 6MV1500GX type Sanyo capacitors. With
Rs=5mV, the maximum ESR becomes 9.5mV which is
equivalent to ≈ 4 caps. Another important consideration
is that if a trace is being used to implement the resistor,
the power dissipated by the trace increases the case
temperature of the output capacitors which could seri-
ously effect the life time of the output capacitors.
Rev. 1.6
07/16/02
www.irf.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IRU3018.PDF ] | |
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