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PDF MC100E016 Data sheet ( Hoja de datos )
| Número de pieza | MC100E016 | |
| Descripción | 8-Bit Synchronous Binary Up Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8ĆBit Synchronous Binary
Up Counter
MC10E016
MC100E016
The MC10E/100E016 is a high-speed synchronous, presettable,
cascadable 8-bit binary counter. Architecture and operation are the same
as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown
in the logic symbol.
The counter features internal feedback of TC, gated by the TCLD
(terminal count load) pin. When TCLD is LOW (or left open, in which case
it is pulled LOW by the internal pull-downs), the TC feedback is disabled,
and counting proceeds continuously, with TC going LOW to indicate an
all-one state. When TCLD is HIGH, the TC feedback causes the counter
to automatically reload upon TC = LOW, thus functioning as a
programmable counter. The Qn outputs do not need to be terminated for
the count function to operate properly. To minimize noise and power,
unused Q outputs should be left unterminated.
8-BIT SYNCHRONOUS
BINARY UP COUNTER
• 700MHz Min. Count Frequency
• 1000ps CLK to Q, TC
• Internal TC Feedback (Gated)
• 8-Bit
• Fully Synchronous Counting and TC Generation
• Asynchronous Master Reset
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
PE CE P7 P6 P5 VCCO TC
25 24 23 22 21 20 19
MR 26
18 Q7
CLK 27
17 Q6
TCLD 28
16 VCC
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
FUNCTION TABLE
CE PE TCLD MR CLK
XL X L Z
LH L L Z
LH H L Z
HH X L Z
X X X L ZZ
XX X H X
Z = clock pulse (low to high);
ZZ = clock pulse (high to low)
Function
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
VEE 1
15 Q5
NC 2
PIN NAMES
14 VCCO
Pin
P0 3
13 Q4
P1 4
12 Q3
5 6 7 8 9 10 11
P2 P3 P4 VCCO Q0 Q1 Q2
P0 – P7
Q0 – Q7
CE
PE
MR
CLK
TC
TCLD
Function
Parallel Data (Preset) Inputs
Data Outputs
Count Enable Control Input
Parallel Load Enable Control Input
Master Reset
Clock
Terminal Count Output
TC-Load Control Input
* All VCC and VCCO pins are tied together on the die.
12/93
© Motorola, Inc. 1996
2–1
REV 2
1 page  
MC10E016 MC100E016
Applications Information (continued)
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not
the case estimates of these delays need to be added to
the calculations.
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 2
below illustrates the input conditions necessary for utilizing the
E016 as a programmable divider set up to divide by 113.
HL L L HHHH
P7 P6 P5 P4 P3 P2 P1 P0
H PE
L CE
H TCLD
CLK
TC
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Figure 2. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply subtracts
the binary equivalent of the desired divide ratio from the binary
value for 256. As an example for a divide ratio of 113:
Pn’s = 256 – 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 2 will
result in the waveforms of Figure 3. Note that the TC output is
used as the divide output and the pulse duration is equal to a
Table 1. Preset Values for Various Divide Ratios
Divide
Ratio
2
3
4
5
•
•
112
113
114
•
•
254
255
256
Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1 P0
HHHHHHH L
HHHHHH L H
HHHHHHL L
HHHHH L HH
••••••••
••••••••
HL LHL L L L
HL L LHHHH
HL L LHHHL
••••••••
••••••••
L L L L L LHL
L L L L L L LH
LLLLLLLL
full clock period. For even divide ratios, twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256 inclusive. If divide ratios of greater than 256 are needed
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
Clock
PE
TC
Load
1001 0000 1001 0001 1111 1100 1111 1101 1111 1110
1111 1111
•••
•••
Load
•••
DIVIDE BY 113
Figure 3. Divide by 113 E016 Programmable Divider Waveforms
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC100E016.PDF ] | |
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