PDF ML7033 Data sheet ( Hoja de datos )

Número de pieza	ML7033
Descripción	Dual-Channel Line Card CODEC
Fabricantes	LAPIS
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No Preview Available ! ML7033 Dual-Channel Line Card CODEC FEDL7033-04 Issue Date: Oct. 13, 2011 GENERAL DESCRIPTION The ML7033 is a 2-channel PCM CODEC CMOS IC designed for Central Office (CO) and Customer Premise Equipment (CPE) environments. The ML7033 device contains 2-channel analog-to-digital (A/D) and digital-to-analog (D/A) converters with multiplexed PCM input and output. The ML7033 is designed for single-rail, low power applications. The high integration of the ML7033 reduces the number of external components and overall board size. The ML7033 is best suited for line card applications and provides an easy interface to subscriber line interface circuits (SLIC’s), in particular the Intersil RSLICTM series. FEATURES  Seamlessly interfaces with Intersil RSLICTM series devices  Single 5 volt power supply (4.75 V to 5.25 V)  - ADC and DAC  PCM format: µ-law/A-law (ITU-T G.711 compliant), 14-bit linear (2’s complement)  Optional wideband filter for V.90 data modem applications  Low power consumption - 2-channel operating mode: 115 mW (typical) 180 mW (max) - 1-channel operating mode: 80 mW (typical) 115 mW (max) - Power-down mode: 0.1 mW (typical) 0.25 mW (max); PDN pin = logic “0”  Power-on reset  Dual programmable tone generators (300 Hz to 3400 Hz; 10 Hz intervals; 0.1 dB intervals) - Call progress tone, DTMF tone  Ringing tone generator (15 Hz to 50 Hz; 1Hz intervals; 0.1 dB intervals)  Pulse metering tone generator (12 kHz, 16 kHz; gain level selectable)  Call ID tone generator (ITU-T V.23, Bell 202)  Analog and digital loop back test modes  Time-slot assignment  Serial MCU interface  Master clock: 2.048 MHz/4.096 MHz selectable  Serial PCM transmission data rate: 256 kbps to 4096 kbps  Adjustable transmit/receive gain (1 dB intervals)  Built-in reference voltage generator  Differential or single-ended analog output selectable  Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Ordering Part number: ML7033GA) 1/52 1 page FEDL7033-04 ML7033 Pin Symbol Type Description 38 VDDD — Power Supply for Internal Digital Circuit 39 MCK I Master Clock (2.048/4.096 MHz) 40 BCLK I PCM Data Shift Clock 41 DG — Digital Ground 42 PCMIN I PCM Data Input 43 PCMOSY O PCM Data Output Indicator for Time-Slot Assignment 44 PCMOUT O PCM Data Output 45 XSYNC I Transmit Synchronizing Clock Input 46 RSYNC I Receive Synchronizing Clock Input 47 RESET I Reset for Control Register 48 N.C — (Leave unconnected) 49 N.C — (Leave unconnected) 50 PDN I Power-down Control 51 TEST I LSI Manufacturer’s Test Input (keep logic “0”) 52 DG — Digital Ground 53 BSEL1 O Output for SLIC1 Battery Select 54 ALM1 I Input from SLIC1 Thermal Shut Down Alarm Detector 55 DET1 I Input from SLIC1 Switch Hook, Ground Key or Ring Trip Detector 56 E0_1 O Output for SLIC1 Detector Mode Selection 57 F0_1 O Mode Control Output to SLIC1 F0 58 F1_1 O Mode Control Output to SLIC1 F1 59 F2_1 O Mode Control Output to SLIC1 F2 60 SWC1 O Output for SLIC1 Uncommitted Switch Control 61 VDDD — Power Supply for Internal Digital Circuit 62 VDDA — Power Supply for Internal Analog Circuit 63 AIN1P I CH1 Transmit Op-amp Input Positive 64 N.C — (Leave unconnected) Note: In this datasheet, “1” and “2” in names for pins which respectively exist for CH1 and CH2 are often substituted by “n” (in a small letter). Ex) GSX1, GSX2 AOUT1N, AOUT2N DET1, DET2  GSXn  AOUTnN  DETn 5/52 5 Page FEDL7033-04 ML7033 AC Characteristics (Continued) (VDD = 4.75 to 5.25 V, Ta = –40 to +85C) Condition Parameter Symbol Freq. Level Min. Typ. Max. Unit (Hz) (dBm0) Analog input = SGC1 NIDLET — — AINn to PCMOUT — 9 15 Gain = 1 -law) Idle Channel Noise NIDLER — PCMIN = ‘FF’h (-law) dBm0 PCMIN = ‘D5’h (A-law) — PCMIN = all ‘0’ (linear)1 — 4 10 PCMIN to AOUTn Absolute Level (Initial Difference) GSXn to PCMOUT VDD = 5 V, Ta = 25C 0.511 0.548 0.587 AVT/AVR PCMIN to AOUTn Vrms 1020 0 (Single-ended) 0.806 0.835 0.864 VDD = 5 V, Ta = 25C Absolute Level (Deviation of Temperature and Power) AVTT AVRT VDD = 4.75 to 5.25 V Ta = –40 to 85C –0.3 –0.3 — — 0.3 dB 0.3 Absolute Delay TD 1020 0 A to A Mode BCLK = 2048 kHz — 0.58 0.6 ms TGD T1 500 — 0.26 0.75 TGD T2 600 — 0.16 0.35 Transmit Group Delay TGD T3 1000 0 2 — 0.02 0.125 ms TGD T4 2600 — 0.05 0.125 TGD T5 2800 — 0.07 0.75 TGD R1 500 — 0.00 0.75 TGD R2 600 — 0.00 0.35 Receive Group Delay TGD R3 1000 0 2 — 0.00 0.125 ms TGD R4 2600 — 0.09 0.125 TGD R5 2800 — 0.12 0.75 Cross Talk Attenuation CRT CRR CRCH 1020 0 Trans to Receive 75 83 — Receive to Trans 75 80 — dB Channel to Channel 75 78 — Discrimination 4.6 to DIS 72k 0 0 to 4 kHz 30 32 — dB Out of Band Spurious OBS 300 to 3.4K 0 4.6 to 1000 kHz — –37.5 –35 dB Signal Frequency Distortion SFDT SFDR 1020 0 0 to 4 kHz — –50 –40 dBm0 — –48 –40 Intermodulation Distortion IMDT fa = 470 IMDR fb = 320 –4 2 fa – fb — –50 –40 dBm0 — –54 –40 PSRT1 0 to 4k 40 44 — Power Supply Noise Rejection Ratio PSRT2 4 to 50k 100 PSRR1 0 to 4k mVrms 3 50 55 — dB 40 45 — PSRR2 4 to 50k 1 C-message filter used 2 Minimum value of the group delay distortion 3 Under idle channel noise 50 56 — 11/52 11 Page

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