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PDF LTC2311-16 Data sheet ( Hoja de datos )
| Número de pieza | LTC2311-16 | |
| Descripción | 5Msps Differential Input ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2311-16 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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FEATURES
LTC2311-16
16-Bit, 5Msps
Differential Input ADC with Wide
Input Common Mode Range
DESCRIPTION
nn 5Msps Throughput Rate
nn ±3LSB INL (Typ), ±8LSB INL Guaranteed
nn Guaranteed 16-Bit, No Missing Codes
nn 8VP-P Differential Inputs with Wide Input Common
Mode Range
nn 81dB SNR (Typ) at fIN = 2.2MHz
nn –90dB THD (Typ) at fIN = 2.2MHz
nn Guaranteed Operation –40°C to 125°C
nn Single 3.3V or 5V Supply
nn Low Drift (20ppm/°C Max) 2.048V or 4.096V Internal
Reference with 1.25V External Reference Input
nn 1.8V to 2.5V I/O Voltages
nn CMOS or LVDS SPI-Compatible Serial I/O
nn Power Dissipation 50mW at VDD = 5V (Typ)
nn Small 16-Lead (4mm × 5mm) MSOP Package
APPLICATIONS
nn High Speed Data Acquisition Systems
nn Communications
nn Remote Data Acquisition
nn Imaging
nn Optical Networking
nn Automotive
nn Multiphase Motor Control
The LTC®2311-16 is a low noise, high speed 16-bit
successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2311-
16 has an 8VP-P differential input range, making it ideal
for applications which require a wide dynamic range with
high common mode rejection. The LTC2311-16 achieves
±3LSB INL typical, no missing codes at 16 bits and 81dB
SNR typical.
The LTC2311-16 has an onboard low drift (20ppm/°C max)
2.048V or 4.096V temperature-compensated reference and
provides an external 1.25V buffered reference input. The
LTC2311-16 also has a high speed SPI-compatible serial
interface that supports CMOS or LVDS. The fast 5Msps
throughput with one-cycle latency makes the LTC2311-16
ideally suited for a wide variety of high speed applications.
The LTC2311-16 dissipates only 50mW with a 5V supply
and offers nap and sleep modes to reduce the power
consumption to 5μW for further power savings during
inactive periods.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
IN+, IN–
ARBITRARY
DIFFERENTIAL
25Ω
0V 0V
BIPOLAR
UNIPOLAR
25Ω
0V 0V
3.3V OR 5V
32k Point FFT fSMPL = 5Msps, fIN = 2.2MHz
1µF
VDD REFOUT
AIN+
10µF
0
SNR = 81.6dB
–20
THD = –90dB
SINAD = 81.1dB
SFDR = 96dB
–40
47pF
LTC2311-16
REFIN
10µF
–60
–80
AIN–
CMOS/LVDS
GND
SDO
SCK
CNV
OVDD
LVDS OR CMOS
CONFIGURABLE
I/O
1.8V TO 2.5V
1µF
–100
–120
–140
0
0.5 1 1.5
FREQUENCY (MHz)
2 2.5
231116 TA01b
231116 TA01a
231116fa
For more information www.linear.com/LTC2311-16
1
1 page  
LTC2311-16
D IGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
CMOS Digital Inputs and Outputs
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Digital Input Current
CIN Digital Input Capacitance
VOH High Level Output Voltage
VOL Low Level Output Voltage
IOZ Hi-Z Output Leakage Current
ISOURCE Output Source Current
ISINK Output Sink Current
LVDS Digital Inputs and Outputs
VIN = 0V to OVDD
IO = –500µA
IO = 500µA
VOUT = 0V to OVDD
VOUT = 0V
VOUT = OVDD
l 0.8 • OVDD
l
l –10
0.2 • OVDD
10
5
l OVDD – 0.2
l
0.2
l –10
10
–10
10
V
V
μA
pF
V
V
µA
mA
mA
VID
LVDS Differential Input Voltage
100Ω Differential Termination, OVDD = 2.5V l
240
600
VIS
LVDS Common Mode Input Voltage 100Ω Differential Termination, OVDD = 2.5V l
1
1.45
VOD
LVDS Differential Output Voltage
100Ω Differential Load, LVDS Mode,
OVDD = 2.5V
l 100 250 300
VOS LVDS Common Mode Output Voltage 100Ω Differential Load, LVDS Mode,
OVDD = 2.5V
l 0.85
1.2
1.4
VOD_LP
Low Power LVDS Differential Output 100Ω Differential Load, Low Power,
Voltage
LVDS Mode, OVDD = 2.5V
l 50
125 200
VOS_LP
Low Power LVDS Common Mode
Output Voltage
100Ω Differential Load, Low Power,
LVDS Mode, OVDD = 2.5V
l 0.9 1.2 1.4
mV
V
mV
V
mV
V
For more information www.linear.com/LTC2311-16
231116fa
5
5 Page 
FUNCTIONAL BLOCK DIAGRAM
LTC2311-16
CMOS I/O Mode
4 VDD
6 AIN+
7 AIN–
+
S/H
–
GND
1, 5, 8, 11, 17
3 REFOUT
G
REFIN
2
9 CNV
LDO
16-BIT
SAR ADC
1.25V REF
TIMING CONTROL
LOGIC
LVDS/CMOS
TRI-STATE
SERIAL OUTPUT
SDO+ 14
OVDD 12
CMOS/LVDS 10
LVDS/CMOS
RECEIVERS
SCK+ 16
231116 BDa
LVDS I/O Mode
4 VDD
6 AIN+
7 AIN–
+
S/H
–
GND
1, 5, 8, 11, 17
3 REFOUT
G
REFIN
2
9 CNV
LDO
16-BIT
SAR ADC
1.25V REF
TIMING CONTROL
LOGIC
LVDS/CMOS
TRI-STATE
SERIAL OUTPUT
SDO+
SDO–
14
13
OVDD 12
CMOS/LVDS 10
LVDS/CMOS
RECEIVERS
SCK+ 16
SCK– 15
231116 BDb
For more information www.linear.com/LTC2311-16
231116fa
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet LTC2311-16.PDF ] | |
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