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PDF MR36V08G57C Data sheet ( Hoja de datos )
| Número de pieza | MR36V08G57C | |
| Descripción | P2ROM | |
| Fabricantes | LAPIS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MR36V08G57C (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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MR36V08G57C
P2ROM262,144–Page × 1,024 x 32–Bit (LVNROM)
FEDR36V08G57C-002-02
Issue Date: Sep. 15, 2010
FEATURES
Memory Configuration
• 262,144 x 1,024 x 32 bit
• Multiplexed Command/Address/Data
Page Read Operation
• Page Size
: 4,096 byte
• Random access time : 1.0us (max) for block read
1.8us (max) for random read
• Sequential Read : 40ns (min)
• Read Mode
Continuous Read : no wait for next page.
Page Read
: need wait time for next page
Power Supply Voltage
• Vcc = 3.0 V to 3.6 V
PACKAGES
·70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor’s technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits over
the other non-volatile technologies, which include the
following;
· Short lead time, since the P2ROM is programmed at the final
stage of the production process, a large P2ROM inventory
"bank system" of un-programmed packaged products are
maintained to provide an aggressive lead-time and minimize
liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom mask
for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
· Custom Marking is available at no additional charge.
PIN CONFIGURATION (TOP VIEW)
Vcc 1
Vss 2
NC 3
NC 4
I E# 5
NC 6
NC 7
NC 8
NC 9
NC 10
NC 11
NC 12
NC 13
Vss 14
CE# 15
Vss 16
Vss 17
Vss 18
Vcc 19
Vss 20
NC 21
NC 22
NC 23
CLE 24
ALE 25
STE 26
NC 27
RST# 28
NC 29
RD/BY 30
Vss 31
D27 32
D19 33
D11 34
D3 35
70 D28
69 D20
68 D12
67 D4
66 D29
65 D21
64 D13
63 D5
62 D30
61 D22
60 D14
59 D6
58 D31
57 D23
56 D15
55 D7
54 OE#
53 NC
52 NC
51 Vcc
50 Vss
49 Vss
48 D0
47 D8
46 D16
45 D24
44 D1
43 D9
42 D17
41 D25
40 Vcc
39 D2
38 D10
37 D18
36 D26
70-pin SSOP
PDDC400565 1/14
1 page  
FEDR36V08G57C-002-02
MR36V08G57C / P2ROM
STATUS OUTPUT
The lower 8bits, D7 to D0, and another 8bits, D23 to D16, of the data outputs are used to output the status bits.
Other bits of the data outputs fixed “low” during status output.
Status Output Bit
D7 (D23)
D6 (D22)
D5 (D21)
D4 (D20)
D3 (D19)
D2 (D18)
D1 (D17)
D0 (D16)
Status value
0
Ready/Busy
0
CMD End
CMD Error
0
0
0
NOTE
—
This field indicates RD/BY output, Ready = H and Busy = L.
This status value is the same behavior with the RD/BY output signal.
—
This field indicates command operation status. “H” indicates the command
operation is completed, and “L” indicates the command operation is in
process.
This field indicates command input status. “H” indicates an error command
input such as invalid command code or invalid address. “L” indicates a
correct command input.
—
—
—
PDDC400565 5/14
5 Page 
TIMING CHART (RESET)
FEDR36V08G57C-002-02
MR36V08G57C / P2ROM
PDDC400565 11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MR36V08G57C.PDF ] | |
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