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PDF MR36V02G54B Data sheet ( Hoja de datos )
| Número de pieza | MR36V02G54B | |
| Descripción | P2ROM | |
| Fabricantes | LAPIS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MR36V02G54B (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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MR36V02G54B
P2ROM64M–Word × 32–Bit Page Mode
FEATURES
· 64Mx32 or 128Mx16-bit
electrically switchable configuration
· Page size of 8-word x 32-Bit or 16-word x 16-Bit
· 3.0 V to 3.6 V power supply
· Random Access time
105 ns MAX
· Page Access time
25 ns MAX
· Operating current 100 mA MAX
· Standby current 50 mA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
·70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits
over the other non-volatile technologies, which include the
following;
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
· Custom Marking is available at no additional charge.
FEDR36V02G54B-002-01
Issue Date: Oct. 01, 2008
PIN CONFIGURATION (TOP VIEW)
Vcc 1
70 D28
Vss 2
69 D20
A24 3
A23 4
A22 5
A21 6
68 D12
67 D4
66 D29
65 D21
A20 7
64 D13
A19 8
63 D5
A18 9
A17 10
A16 11
A15 12
62 D30
61 D22
60 D14
59 D6
A14 13
A25 14
CE# 15
A13 16
58 D31
57 D23
56 D15
55 D7
A12 17
54 OE#
A11 18
53 A_1
Vcc 19
Vss 20
A1 21
A2 22
A3 23
52 A0
51 Vcc
50 WORD#
49 Vss
48 D0
A4 24
47 D8
A5 25
A6 26
A7 27
A8 28
46 D16
45 D24
44 D1
43 D9
A9 29
42 D17
A10 30
41 D25
Vss 31
D27 32
D19 33
40 Vcc
39 D2
38 D10
D11 34
37 D18
D3 35
36 D26
70-pin SSOP
1/9
1 page  
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
tC
tC
Address
CE#
tCE
tOE
tASK
tACC
tOH
tOH
tCHZ
OE#
Dout
tACC
Hi-Z
Valid Data
tOHZ
Valid Data
Hi-Z
Page Access Mode Read Cycle
A3 to A25
tC
A-1 to A2 (X16 mode)
A0 to A2 (X32 mode)
CE#
OE#
Dout
tCE
tCSK
tOE
tACC
Hi-Z
tPC tPC
tOH
tPAC
tPAC
tCHZ
tOHZ
Hi-Z
5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MR36V02G54B.PDF ] | |
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