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PDF MR27V3252J Data sheet ( Hoja de datos )
| Número de pieza | MR27V3252J | |
| Descripción | P2ROM | |
| Fabricantes | LAPIS | |
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MR27V3252J
P2ROM2M–Word × 16–Bit or 4M–Word × 8–Bit Page Mode
FEDR27V3252J-002-02
Issue Date: Oct. 01, 2008
FEATURES
· 2,097,152-word × 16-bit / 4,194,304-word × 8-bit electrically
switchable configuration
· Page size of 8-word x 16-Bit or 16-word x 8-Bit
· 3.0 V to 3.6 V power supply
· Random Access time.....................70 ns MAX
· Page Access time ..........................25 ns MAX
· Operating current ..........................50 mA MAX
· Standby current .............................10 µA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR27V3252J-xxxMA
44-pin plastic SOP (SOP44-P-600-1.27-K)
· MR27V3252J-xxxTN
48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and
OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory
with minimal effect on the production throughput. The cost
is included in the unit price.
· Custom Marking is available at no additional charge.
PIN CONFIGURATION (TOP VIEW)
NC 1
A18 2
A17 3
A7 4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
CE# 12
VSS 13
OE# 14
D0 15
D8 16
D1 17
D9 18
D2 19
D10 20
D3 21
D11 22
44SOP
44 A20
43 A19
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 D15/A–1
30 D7
29 D14
28 D6
27 D13
26 D5
25 D12
24 D4
23 VCC
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
A19 9
A20 10
NC 11
NC 12
NC 13
NC 14
NC 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
48 A16
47 BYTE#
46 VSS
45 D15/A–1
44 D7
43 D14
42 D6
41 D13
40 D5
39 D12
38 D4
37 VCC
36 D11
35 D3
34 D10
33 D2
32 D9
31 D1
30 D8
29 D0
28 OE#
27 VSS
26 CE#
25 A0
48TSOP(Type-I)
1/9
1 page  
FEDR27V3252J-002-02
MR27V3252J / P2ROM
TIMING CHART (READ CYCLE)
RANDOM ACCESS MODE READ CYCLE
tC
tC
Address
CE#
tCE
tOE
tACC
tOH
tOH
tCHZ
OE#
Dout
tACC
Hi-Z
Valid Data
tOHZ
Valid Data
Hi-Z
PAGE ACCESS MODE READ CYCLE
tC
A3 to A20
A-1 to A2 (Byte mode)
A0 to A2 (Word mode)
CE#
OE#
Dout
tCE
tOE
tACC
Hi-Z
tPC tPC
tOH
tPAC
tPAC
tCHZ
tOHZ
Hi-Z
5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MR27V3252J.PDF ] | |
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