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PDF MR27V1641L Data sheet ( Hoja de datos )

Número de pieza MR27V1641L
Descripción P2ROM
Fabricantes LAPIS 
Logotipo LAPIS Logotipo



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No Preview Available ! MR27V1641L Hoja de datos, Descripción, Manual

MR27V1641L
16M–Word × 1–Bit Serial Production Programmed ROM (P2ROM)
FEDR27V1641L-002-04
Issue Date: Apr. 1, 2009
GENERAL DESCRIPTION
The MR27V1641L is a 16 Mbit Production Programmed Read-Only Memory, which is configured as 16,777,216
word × 1-bit. The MR27V1641L supports a simple read operation using a single 3.3V power supply and a Serial
Peripheral Interface (SPI) compatible serial bus.
The MR27V1641L have data programmed and have functions tested at LAPIS Semiconductor factory. (Using the
DC pins for the programming function is NOT allowed.)
FEATURES
· 16,777,216-word × 1-bit configuration
· +3.0 V to 3.6 V power supply
· Access time
33 MHz serial clock (FAST-READ)
20 MHz serial clock (READ)
· Read Identification Instruction
· Active read current
25 mA MAX (FAST-READ)
20 mA MAX (READ)
· Standby current
50 µA MAX
· Serial Clock Input and Data Input/Output
· Input Data Format
1-byte command code, 3-byte address, 1-byte dummy
(FAST-READ)
1-byte command code, 3-byte address
(READ)
PIN CONFIGURATION (TOP VIEW)
NC
VCC
NC
DC
NC
NC
#CS
SO
1
2
3
4
5
6
7
8
16 SCLK
15 SI
14 NC
13 NC
12 NC
11 NC
10 VSS
9 NC
16SOP
PACKAGES
· MR27V1641L-xxxMP
16-pin plastic SOP (P-SOP16-375-1.27-K)
PIN DESCRIPTIONS
Pin name
#CS
SI
SO
SCLK
VCC
VSS
DC
NC
Functions
Chip Select
Serial Data Input
Serial Data Output
Clock Input
Power supply voltage
Ground
Don’t care ( 0v - Vcc )
<for reference> Program power supply voltage Vpp under Programming operation
No connection
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1 page




MR27V1641L pdf
FEDR27V1641L-002-04
MR27V1641L / P2ROM
DEVICE OPERATION
1. Command “03h” or “0Bh” makes this LSI become and keep active mode until next #CS High.
2. Incorrect command makes this LSI become and keep standby mode until next #CS Low. In standby mode, SO
pin is High-Z.
3. At Power-up, the device must not be selected (that is #CS must follow the voltage applied on Vcc) until Vcc
reaches the operating value.
COMMAND DESCRIPTION
1. Read Array
This command consists of the 4-byte code. The 1st code is a command which decides if the device becomes
standby or active mode. The 1st code “03h”activates the device. The 2nd code to the 4th code are address.
2. Fast-Read Array
This command consists of the 5-byte code. The 1st code is a command which decides if the device becomes
standby or active mode. The 1st code “0Bh”activates the device. The 2nd code to the 4th code are address. The 5th
code is a dummy cycle.
3. Read Identification Array
This command consists of the 1-byte code. The 1st code is a command which decides if the device becomes
standby or active mode. The 1st code “9Fh”activates the device.
4. Standby
When #CS is high , the device is put in standby mode at the next rising edge of SCLK. Maximum standby
current is 50uA. When the above-mentioned 1st code is incorrect command , the device is put in standby mode
at the next rising edge of SCLK.
DATA SEQUENCE
The data is serially sent out through SO pin, synchronized with the falling edge of SCLK. Meanwhile input data is
also serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input
and output data are bit7 (MSB) first, bit6, bit5, …, and bit0(LSB).
ADDRESS SEQUENCE
The address assignment is described at the COMMAND DEFINITION on page 2 or 3.
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5 Page





MR27V1641L arduino
FEDR27V1641L-002-04
MR27V1641L / P2ROM
Fast Read Array Timing Waveform
#CS
SCLK
SI
SO
*note1
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3
1st byte Command
2nd byte AD1
Hi-Z
#CS
SCLK
SI
SO
*note2
BIT 1 BIT 0
Don’t Care
5th byte DUMMY
Hi-Z
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5
1st data output
2nd data output
#CS
SCLK
SI
SO BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7
Hi-Z
(N-1)th data output
Nth data output
(N+1)th data output
Note:
1. Input data are latched at SCLK-rising edge.
2. Data-output starts at SCLK-falling edge in bit0 of the 5th byte.
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