|
|
PDF CY7C1516V18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1516V18 | |
| Descripción | 1.8V Synchronous Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1516V18 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CY7C1516V18, CY7C1527V18
CY7C1518V18, CY7C1520V18
72-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 300 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Synchronous internally self-timed writes
■ 1.8V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4V–VDD)
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1516V18 – 8M x 8
CY7C1527V18 – 8M x 9
CY7C1518V18 – 4M x 18
CY7C1520V18 – 2M x 36
Functional Description
The CY7C1516V18, CY7C1527V18, CY7C1518V18, and
CY7C1520V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1516V18
and two 9-bit words in the case of CY7C1527V18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1516V18 and
CY7C1527V18. On CY7C1518V18 and CY7C1520V18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518V18 and two 36-bit words in the case of
CY7C1520V18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
Maximum Operating Frequency
300
Maximum Operating Current
x8 900
x9 900
x18 940
x36 1080
278 MHz
278
860
860
860
985
250 MHz
250
800
800
800
900
200 MHz
200
700
700
700
735
167 MHz
167
650
650
650
650
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05563 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 13, 2008
[+] Feedback
1 page  
CY7C1516V18, CY7C1527V18
CY7C1518V18, CY7C1520V18
Pin Configuration (continued)
The pin configuration for CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 follow. [1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1518V18 (4M x 18)
123456789
A CQ A
A
R/W
BWS1
K
NC LD
A
B NC DQ9 NC A NC K BWS0 A NC
C
NC NC NC VSS
A
A0
A VSS NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
L
NC DQ15 NC
VDDQ
VSS
VSS
VSS VDDQ NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
N NC NC DQ16 VSS A A A VSS NC
P
NC
NC DQ17
A
A
C
A
A NC
R
TDO
TCK
A
A
A
C
A
A
A
10
A
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1520V18 (2M x 36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ VSS/144M
A
R/W
BWS2
K
BWS1
LD
A
A CQ
B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8
C
NC NC DQ28 VSS
A
A0
A VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS VDDQ NC DQ15 DQ6
F
NC DQ30 DQ21 VDDQ VDD
VSS
VDD
VDDQ
NC
NC DQ5
G
NC DQ31 DQ22 VDDQ VDD
VSS
VDD
VDDQ
NC
NC DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC DQ13 DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC DQ12 DQ3
L
NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC
NC DQ2
M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
N NC DQ35 DQ25 VSS A A A VSS NC NC DQ10
P
NC
NC DQ26
A
A
C
A
A
NC
DQ9
DQ0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 38-05563 Rev. *E
Page 5 of 31
[+] Feedback
5 Page 
CY7C1516V18, CY7C1527V18
CY7C1518V18, CY7C1520V18
Write Cycle Descriptions
The write cycle description table for CY7C1527V18 follows. [2, 8]
BWS0
L
L
H
K
L–H
–
L–H
K Comments
– During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
– No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1520V18 follows. [2, 8]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Document Number: 38-05563 Rev. *E
Page 11 of 31
[+] Feedback
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1516V18.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1516V18 | 1.8V Synchronous Pipelined SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |