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PDF CY7C128A Data sheet ( Hoja de datos )
| Número de pieza | CY7C128A | |
| Descripción | 2K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C128A
2K x 8 Static RAM
Features
I Automatic power-down when deselected
I CMOS for optimum speed/power
I High speed
Ë 20 ns
I Low active power
Ë 660 mW (commercial)
I Low standby power
Ë 110 mW (20 ns)
I TTL-compatible inputs and outputs
I Capable of withstanding greater than 2001V electrostatic
discharge
I Available in Pb-free 24-pin Molded SOJ, non Pb-free 24-pin
(300-Mil) Molded DIP
Logic Block Diagram
Functional Description
The CY7C128A is a high-performance CMOS static RAM
organized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), and active LOW
Output Enable (OE) and tri-state drivers. The CY7C128A has an
automatic power-down feature, reducing the power consumption
by 83% when deselected.
Writing to the device is accomplished when the Chip Enable (CE)
and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O0 through I/O7) is written into the
memory location specified on the address pins (A0 through A10).
Reading the device is accomplished by taking Chip Enable (CE)
and Output Enable (OE) LOW while Write Enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the eight
I/O pins.
The I/O pins remain in high-impedance state when Chip Enable
(CE) or Output Enable (OE) is HIGH or Write Enable (WE) is
LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
A10
A9
A8
A7
A6
A5
A4
CE
WE
OE
INPUT BUFFER
128 x 16 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
A3 A2 A1 A0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
C128A–1
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05028 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 19, 2010
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CY7C128A
Switching Waveforms
Read Cycle No. 1[9, 10]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
Read Cycle No. 2[9, 11]
CE
t RC
DATA VALID
C128A–6
OE
DATA OUT
VCC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
HIGH IMPEDANCE
tLZCE
tPU
50%
Write Cycle No. 1 (WE Controlled)[8]
DATA VALID
tHZOE
tHZCE
HIGH
IMPEDANCE
tPD
50%
ICC
ISB
C128A–7
ADDRESS
CE
WE
DATA IN
DATA I/O
tWC
tSCE
tAW
tSA
DATA UNDEFINED
tPWE
tHA
tSD
DATAIN VALID
tHD
tHZWE
tLZWE
HIGH IMPEDANCE
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected. OE, CE = VIL.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05028 Rev. *B
C128A–8
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