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PDF ADT7473 Data sheet ( Hoja de datos )
| Número de pieza | ADT7473 | |
| Descripción | Remote Thermal Monitor and Fan Control | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADT7473
Remote Thermal Monitor
and Fan Control
The ADT7473/ADT7473−1 controller is a thermal monitor and
multiple PWM fan controller for noise sensitive or power sensitive
applications requiring active system cooling. The
ADT7473/ADT7473−1 can drive a fan using either a low or high
frequency drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure and
control the speed of up to four fans so they operate at the lowest
possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique dynamic TMIN control mode enables the
system thermals/acoustics to be intelligently managed. The
effectiveness of the system’s thermal solution can be monitored using
the THERM input. The ADT7473/ADT7473−1 also provide critical
thermal protection to the system using the bidirectional THERM pin
as an output to prevent system or component overheating.
Features
• Controls and Monitors Up to 4 Fans
• High and Low Frequency Fan Drive Signal
• 1 On-Chip and 2 Remote Temperature Sensors
• Series Resistance Cancellation on the Remote Channel
• Extended Temperature Measurement Range, Up to 191°C
• Dynamic TMIN Control Mode Intelligently Optimizes System
Acoustics
• Automatic Fan Speed Control Mode Controls System Cooling Based
on Measured Temperature
• Enhanced Acoustic Mode Dramatically Reduces User Perception of
Changing Fan Speeds
• Thermal Protection Feature via THERM Output
• Monitors Performance Impact of Intel® Pentium® 4 Processor
• Thermal Control Circuit via THERM Input
• 3-wire and 4-wire Fan Speed Measurement
• Limit Comparison of All Monitored Values
• Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
QSOP−16
CASE 492
PIN ASSIGNMENTS
SCL 1
GND 2
VCC 3
TACH3
PWM2/
SMBALERT
TACH1
4
5
6
TACH2 7
PWM3 8
ADT7473
(Top View)
16 SDA
15 PWM1/XTO
14 VCCP
13 D1+
12 D1−
11 D2+
10 D2−
9 TACH4/GPIO/
THERM/
SMBALERT
SCL 1
GND 2
VCC
TACH3/
ADDR SELECT
PWM2/
THERM_LATCH
TACH1
3
4
5
6
TACH2 7
PWM3/ 8
ADDREN
16 SDA
15 PWM1/XTO
14 VCCP
ADT7473−1 13 D1+
(Top View) 12 D1−
11 D2+
10 D2−
9 TACH4/GPIO/
THERM/
SMBALERT
MARKING DIAGRAMS
ADT747
3ARQZ
#YYWW
ADT
7473−1
ARQZ
#YYWW
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 10
ADT7473
ADT7473−1
ADT7473ARQZ = Specific Device Code
ADT7473−1ARQZ = Specific Device Code
# = Pb-Free Package
YYWW
= Date Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 72 of this data sheet.
1 Publication Order Number:
ADT7473/D
1 page  
ADT7473
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Conditions
Min Typ Max Unit
Digital Input Logic Levels (TACH Inputs)
Input High Voltage, VIH
Maximum Input Voltage
2.0 −
−V
− − 3.6
Input Low Voltage, VIL
Minimum Input Voltage
−−
−0.3 −
0.8 V
−
Hysteresis
− 0.5 − V p-p
Digital Input Logic Levels (THERM) ADTL+
Input High Voltage, VIH
0.75 × VCC
−
−V
Input Low Voltage, VIL
− − 0.8 V
Input High Voltage, VIH
−−−
Input Low Voltage, VIL
VIN = VCC
− ±1 − mA
Input Low Current, IIL
VIN = 0
− ±1 − mA
Input Capacitance, CIN
− 5.0 − pF
Serial Bus Timing (Note 2) (See Figure 2)
Clock Frequency, fSCLK
10 − 400 kHz
Glitch Immunity, tSW
− − 50 ns
Bus Free Time, tBUF
4.7 −
− ms
SCL Low Time, tLOW
4.7 −
− ms
SCL High Time, tHIGH
4.0 − 50 ms
SCL, SDA Rise Time, tr
−
−
1,000
ns
SCL, SDA Fall Time, tf
− − 300 ms
Data Setup Time, tSU; DAT
250 −
− ns
Detect Clock Low Timeout, tTIMEOUT
Can be Optionally Disabled
15 − 35 ms
1. All voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA = 25°C and represent most likely parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
2. Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
SCL
SDA
tBUF
PS
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
www.onsemi.com
5
5 Page 
ADT7473
1
SCL
91
9
SDA
0
START BY
MASTER
1 0 1 1 1 0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ACK. BY
FRAME 1
ADT7473/ADT7473−1
FRAME 2
ADT7473/ADT7473−1
SERIAL BUS ADDRESS BYTE
ADDRESS POINTER REGISTER BYTE
SCL (CONTINUED)
1
9
SDA (CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY STOP BY
FRAME 3 ADT7473/ADT7473−1 MASTER
DATA BYTE
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
SCL
91
9
SDA
0
START BY
MASTER
1 0 1 1 1 0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ACK. BY
FRAME 1
ADT7473/ADT7473−1
FRAME 2 ADT7473/ADT7473−1
SERIAL BUS ADDRESS BYTE
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
Figure 18. Writing to the Address Pointer Register Only
1
SCL
91
9
SDA
0
START BY
MASTER
1 0 1 1 1 0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 1
ACK. BY
ADT7473/ADT7473−1
FRAME 2
NO ACK. BY
MASTER
SERIAL BUS ADDRESS BYTE
DATA BYTE FROM ADT7473
STOP BY
MASTER
Figure 19. Reading Data from a Previously Selected Register
Write Operations
The SMBus specification defines several protocols for
various read and write operations. The ADT7473/
ADT7473−1 uses the following SMBus write protocols. The
following abbreviations are used in the diagrams:
S − Start
P − Stop
R − Read
W − Write
A − Acknowledge
A − No Acknowledge
Send Byte
In this operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
For the ADT7473/ADT7473−1, the send byte protocol is
used to write a register address to RAM for a subsequent
single-byte read from the same address. This operation is
illustrated in Figure 20.
12
3 4 56
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
AP
Figure 20. Setting a Register Address for
Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single-byte read without asserting an intermediate stop
condition.
www.onsemi.com
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADT7473.PDF ] | |
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