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PDF MAX2871 Data sheet ( Hoja de datos )
| Número de pieza | MAX2871 | |
| Descripción | 23.5MHz to 6000MHz Fractional/Integer-N Synthesizer/VCO | |
| Fabricantes | Maxim Integrated | |
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MAX2871
EVALUATION KIT AVAILABLE
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
General Description
The MAX2871 is an ultra-wideband phase-locked loop (PLL)
with integrated voltage control oscillators (VCOs) capable
of operating in both integer-N and fractional-N modes.
When combined with an external reference oscillator and
loop filter, the MAX2871 is a high-performance frequency
synthesizer capable of synthesizing frequencies from
23.5MHz to 6.0GHz while maintaining superior phase
noise and spurious performance.
The ultra-wide frequency range is achieved with the
help of multiple integrated VCOs covering 3000MHz to
6000MHz, and output dividers ranging from 1 to 128. The
device also provides dual differential output drivers, which
can be independently programmed to deliver -1dBm to
+8dBm differential output power. Both outputs can be
muted by either software or hardware control.
The MAX2871 is controlled by a 3-wire serial interface and
is compatible with 1.8V control logic. The device is available
in a lead-free, RoHS-compliant, 5mm x 5mm, 32-pin TQFN
package, and operates over an extended -40°C to +85°C
temperature range.
The MAX2871 has an improved feature set and better overall
phase noise and is fully pin- and software- compatible with
the MAX2870.
Applications
●● Wireless Infrastructure
●● Test and Measurement
●● Clock Generation
●● Microwave Radios
Functional Diagram
Benefits and Features
●● Output Binary Buffers/Dividers Enable Extended
Frequency Range
• Divider Ratios of 1/2/4/8/16/32/64/128
• 23.5MHz to 6000MHz
●● High-Performance Phase Frequency Detector (PFD)
and Reference Frequency Reduces Spectral Noise
• PFD Up to 140MHz
• Reference Frequency Up to 210MHz
●● Low Normalized Inband Phase Noise of -230dBc/Hz
Reduces System Noise Floor Contribution
●● Manual/Automatic VCO Selection Permits Fast
Switching
●● Output Phase Reset and Adjustment Allow
Synchronization of Multiple Synthesizers
●● On-Chip Temperature Sensor with 7-Bit ADC Ensures
Optimum VCO Selection
●● Cycle Slip Reduction and Fast Lock Features
Improve Accuracy and Acquisition Time
●● VCO Lock Maintained Over Entire Temperature
Range Provides Glitch-Free Operation
●● Dual Differential Programmable Outputs Maximize
Flexibility of Use
Ordering Information and Typical Application Circuit
appears at end of data sheet.
MAX2871
REF_IN
CLK
DATA
LE
MUX R COUNTER
X2
SPI AND
REGISTERS
INTEGER
FRAC
MODULUS
DIVIDE-BY-2
MUX
VCO
DIV-BY-
1/ 2 /4 /8 /16
N COUNTER
MAIN
MODULATOR
MUX
MUX
LOCK DETECT
CHARGE
PUMP
DIV-BY-
1/ 2 /4 /8
MUX
MUX
LD
CP_OUT
GND_CP
TUNE
RFOUTA_P
RFOUTA_N
RFOUT_EN
RFOUTB_P
RFOUTB_N
19-7106; Rev 2; 5/16
1 page  
MAX2871
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO
SPI TIMING CHARACTERISTICS
(VCC_ = +3V to +3.6V, VGND_ = 0V, TA = -40°C to +85°C. Typical values at VCC_= 3.3V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CLK Clock Period
tCP
Guaranteed by CLK pulse-width
low and high
50
ns
CLK Pulse-Width Low
tCL
25 ns
CLK Pulse-Width High
tCH
25 ns
LE Setup Time
tLES
20 ns
LE Hold Time
tLEH
10 ns
LE Minimum Pulse-Width High
tLEW
20 ns
DATA Setup Time
tDS
25 ns
DATA Hold Time
tDH
25 ns
MUX Valid
tDOT
MUX transition valid after CLK rise
10 ns
Note 2: Production tested at TA = +25°C. Cold and hot are guaranteed by design and characterization.
Note 3: fREF_IN = 100MHz, phase detector frequency = 25MHz, RF output = 6000MHz.
Register setting: 00780000, 00400061, 34011242, F8010003, 638FF1FC, 80400005.
Note 4: Measured single ended with 27nH to VCC_RF into 50Ω load. Power measured with single output enabled. Unused output
has 27nH to VCC_RF with 50Ω termination.
Note 5: VCO phase noise is measured open loop.
Note 6: Measured at 200kHz using a 50MHz Bliley NV108C19554 OCVCXO with 2MHz loop bandwidth. Register setting
801E0000, 8000FFF9, 80005FC2, 6C10000B, 638E80FC, 400005. EV kit loop filter: C2 = 1500pF, C1 = 33pF, R2A = 0Ω,
R2B = 1100Ω, R3 = 0Ω, C3 = open.
Note 7: 1/f noise contribution to the in-band phase noise is computed by using 1/f noise + 10log(10kHz/fOFFSET) +
20log(fRF/1GHz). Register setting: 803A0000, 8000FFF9, 81005F42, F4000013, 6384803C, 001500005.
Note 8: fREF_IN = 50MHz; fPFD = 25MHz; offset frequency = 10kHz; VCO frequency = 4227MHz, output divide-by-2 enabled.
RFOUT = 2113.5MHz; N = 169; loop BW = 40kHz, CP[3:0] = 1111; integer mode.
Note 9: fREF_IN = 50MHz; fPFD = 50MHz; VCO frequency = 4400MHz, fRFOUT_ = 4400MHz; loop BW = 65kHz. Register setting:
002C0000, 200303E9, 80005642, 00000133, 638E82FC, 01400005. EV kit loop filter: C2 = 0.1µF, C1 = 0.012µF,
R2A = 0Ω, R2B = 120Ω, R3 = 250Ω, C3 = 820pF.
www.maximintegrated.com
Maxim Integrated │ 5
5 Page 
MAX2871
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer /VCO
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
LD 25
16 VCC_RF
RFOUT_EN 26
15 RFOUTB_N
GND_DIG 27
14 RFOUTB_P
VCC_DIG 28
REF_IN 29
MAX2871
13 RFOUTA_N
12 RFOUTA_P
MUX 30
11 GND_RF
GND_SD 31
VDD_SD 32
+
EP 10 VCC_PLL
9 GND_PLL
1 2345678
TQFN
Pin Description
PIN NAME
1 CLK
2 DATA
3 LE
4 CE
5 SW
6 VCC_CP
7 CP_OUT
8 GND_CP
9 GND_PLL
10 VCC_PLL
11 GND_RF
12 RFOUTA_P
13 RFOUTA_N
FUNCTION
Serial Clock Input. The data is latched into the 32-bit shift register on the rising edge of the
CLK line.
Serial Data Input. The serial data is loaded MSB first. The 3 LSBs identify the register address.
Load Enable Input. When LE goes high the data stored in the shift register is loaded into the
appropriate latches.
Chip Enable. A logic-low powers the part down and the charge pump becomes high impedance.
Fast-Lock Switch. Connect to the loop filter when using the fast-lock mode.
Power Supply for Charge Pump. Place decoupling capacitors as close as possible to the pin.
Charge-Pump Output. Connect to external loop filter input.
Ground for Charge-Pump. Connect to board ground, not to the paddle.
Ground for PLL. Connect to board ground, not to the paddle.
Power Supply for PLL. Place decoupling capacitors as close as possible to the pin.
Ground for RF Outputs. Connect to board ground plane, not to the paddle.
Open Collector Positive RF Output A. See RFOUTA± and RFOUTB± section in Detailed
Description.
Open Collector Negative RF Output A. See RFOUTA± and RFOUTB± section in Detailed
Description.
www.maximintegrated.com
Maxim Integrated │ 11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet MAX2871.PDF ] | |
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