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PDF AS4C4M16S-6BIN Data sheet ( Hoja de datos )
| Número de pieza | AS4C4M16S-6BIN | |
| Descripción | 64M - (4M x 16 bit) Synchronous DRAM | |
| Fabricantes | Alliance Semiconductor | |
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AS4C4M16S
Confidential
64M – (4M x 16 bit) Synchronous DRAM (SDRAM)
FBGA - Rev 2, May. /2014
Features
Fast access time from clock: 5.4 ns
Fast clock rate: 166 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package
- All parts ROHS Compliant
Overview
The 64Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use. By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Table 1. Key Specifications
AS4C4M16S
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK (max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
-6
6
5.4
42
60
ns
ns
ns
ns
Table 2.Ordering Information
Part Number
Frequency
AS4C4M16S-6BIN
166MHz
AS4C4M16S-6BCN
166MHz
Package
54-Ball FBGA
54-Ball FBGA
Temperature
Industrial
Commercial
Temp Range
-40 ~ 85°C
0 ~ 70°C
B: indicates FBGA package
N: indicates Pb and Halogen Free
Confidential
1
Rev 2.0
May. /2014
1 page  
AS4C4M16S
DQ0-DQ15
NC/RFU
VDDQ
VSSQ
VDD
VSS
Input / Data I/O: The DQ0-15 input and output data are synchronized with the positive
Output edges of CLK. The I/Os are maskable during Reads and Writes.
- No Connect: These pins should be left unconnected.
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V 0.3V )
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
(0V)
Supply Power Supply: +3.3V 0.3V
Supply Ground
Confidential
5 Rev 2.0 May/. 2014
5 Page 
AS4C4M16S
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered, where m
equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask
input data, starting with the clock edge following the last data-in element and ending with the clock edge on
which the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
T0 T1 T2 T3 T4 T5 T6 T7
CLK
DQM
COMMAND
WRITE
NOP
NOP
Precharge
tRP
NOP
NOP
Activate
NOP
ADDRESS
DQ
Bank
Col n
DIN
n
tWR
DIN
N+1
Bank (s)
ROW
Don’t Care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7 Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the write
operation. Once this command is given, any subsequent command can not occur within a time delay of
{(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this
command and the auto precharge function is ignored.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK
COMMAND
Bank A
Activate
NOP
NOP
WRITE A
Auto Precharge
NOP
NOP
tDAL
NOP
NOP
NOP
Bank A
Activate
DQ
DIN A0
DIN A1
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the
Mode register to make SDRAM useful for a variety of different applications. The default values of the
Mode Register after power-up are undefined; therefore this command must be issued at the power-up
sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register.
Two clock cycles are required to complete the write in the mode register (refer to the following figure). The
contents of the mode register can be changed using the same command and the clock cycle
requirements during operation as long as all banks are in the idle state.
Confidential
11 Rev 2.0 May/. 2014
11 Page | ||
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