PDF AS4C256M16D3A-12BIN Data sheet ( Hoja de datos )

Número de pieza	AS4C256M16D3A-12BIN
Descripción	256M x 16 bit DDR3 Synchronous DRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! AS4C256M16D3A-12BIN Revision History 4Gb AS4C256M16D3A-12BIN - 96 ball FBGA PACKAGE Revision Details Rev 1.0 Preliminary datasheet Date May. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -183- Rev. 1.0 May 2016 1 page AS4C256M16D3A-12BIN Figure 3. State Diagram This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail Power applied Power On Reset Procedure Initialization MRS,MPR, Write Leveling Self Refresh from any state RESET ZQCL MRS ZQ ZQCL,ZQCS Calibration Idle REF Refreshing ACT ACT = Active PRE = Precharge PREA = Precharge All MRS = Mode Register Set REF = Refresh RESET = Start RESET Procedure Read = RD, RDS4, RDS8 Read A = RDA, RDAS4, RDAS8 Write = WR, WRS4, WRS8 Write A = WRA, WRAS4, WRAS8 ZQCL = ZQ Calibration Long ZQCS = ZQ Calibration Short PDE = Enter Power-down PDX = Exit Power-down SRE = Self-Refresh entry SRX = Self-Refresh exit MPR = Multi-Purpose Register Automatic Sequence Command Sequence Active Power Down PDX PDE WRITE Writing WRITE A Writing WRITE A Activating Bank Activating WRITE Precharging Precharge Power Down READ READ READ READ A Reading READ A READ A Reading Confidential -583- Rev. 1.0 May 2016 5 Page AS4C256M16D3A-12BIN z Reset Procedure at Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns). 2. Follow Power-up Initialization Sequence step 2 to 11. 3. The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation. Figure 5. Reset Procedure at Power Stable Condition Ta Tb Tc Td Te Tf Tg Th Ti CK# CK VDD VDDQ T=100ns tCKSRX T=500µs RESET# CKE COMMAND Tmin=10ns tIS tIS tXPR tMRD tMRD tMRD tDLLK tMOD Note 1 MRS MRS MRS MRS ZQCL Tj tZQinit Note 1 Tk VALID BA ODT RTT MR2 MR3 MR1 MR0 tIS Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID tIS VALID NOTE 1. From time point Td until Tk NOP or DES commands must be applied between MRS and ZQCL commands. TIME BREAK Don't Care Confidential -1183- Rev. 1.0 May 2016 11 Page

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Número de pieza	Descripción	Fabricantes
AS4C256M16D3A-12BIN	256M x 16 bit DDR3 Synchronous DRAM	Alliance Semiconductor

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