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Número de pieza | AS4C128M8D3 | |
Descripción | 1Gb (128M x 8) bit DDR3 Synchronous DRAM | |
Fabricantes | Alliance Semiconductor | |
Logotipo | ||
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REVISION HISTORY
Revision
Rev. 1.0
Rev. 2.0
Rev 3.0
Description
Initial Issue
Typing error – in Table 2 page 2 – incorrect temperature range
amended to:
- Commercial (Extended)(0 ~ 95°C)
- Industrial (-40 ~ 95°C)
Updated Table 12. Recommended DC Operating Conditions – page
21
Added CL=5 & CL=6 to Table 18 – page 26
Issue Date
February 2014
June 2014
August 2014
Confidential
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1 page AS4C128M8D3
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands
to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination,
and some other events are not captured in full detail.
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
Self
Refresh
from any
state
RESET
ZQCL
MRS
ZQ ZQCL,ZQCS
Calibration
Idle
REF Refreshing
ACT
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
Automatic Sequence
Command Sequence
Active
Power
Down
PDX
PDE
WRITE
Writing
WRITE A
Writing
WRITE A
Activating
Bank
Activating
WRITE
Precharging
Precharge
Power
Down
READ
READ
READ
READ A
Reading
READ A
READ A
Reading
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Rev. 3.0
Aug. /2014
5 Page AS4C128M8D3
Reset Procedure at Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time
10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation.
Figure 5. Reset Procedure at Power Stable Condition
CK#
CK
VDD
VDDQ
Ta Tb Tc Td Te Tf Tg Th Ti
T=100ns
tCKSRX
T=500μs
RESET#
CKE
COMMAND
Tmin=10ns
tIS
tIS tXPR
tMRD
tMRD
tMRD
tDLLK
tMOD
Note 1
MRS
MRS
MRS
MRS
ZQCL
Tj
tZQinit
Note 1
Tk
VALID
BA
ODT
RTT
MR2
MR3
MR1
MR0
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
tIS
VALID
NOTE 1. From time point “Td”until “Tk”NOP or DES commands must be applied between MRS and ZQCL commands.
TIME BREAK
Don't Care
Confidential
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Rev. 3.0
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11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet AS4C128M8D3.PDF ] |
Número de pieza | Descripción | Fabricantes |
AS4C128M8D2 | 128M x 8 bit DDRII Synchronous DRAM | Alliance Semiconductor |
AS4C128M8D3 | 1Gb (128M x 8) bit DDR3 Synchronous DRAM | Alliance Semiconductor |
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