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PDF CY7C1460SV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1460SV25 | |
| Descripción | 36-Mbit (1M x 36/2M x 18) Pipelined SRAM | |
| Fabricantes | Cypress | |
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CY7C1460SV25
CY7C1462SV25
36-Mbit (1M × 36/2M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250 and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ 2.5-V core power supply
■ 2.5-V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ CY7C1460SV25 available in JEDEC-standard Pb-free 100-pin
TQFP package and non Pb-free 165-ball FBGA package.
CY7C1462SV25 available in Pb-free 100-pin TQFP package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460SV25/CY7C1462SV25 are 2.5 V,
1M × 36/2M × 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back to back Read/Write
operations with no wait states. The
CY7C1460SV25/CY7C1462SV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.
CY7C1460SV25/CY7C1462SV25 are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1460SV25 and BWa–BWb for
CY7C1462SV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.6
435
120
167 MHz
3.4
335
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-43804 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 7, 2016
1 page  
CY7C1460SV25
CY7C1462SV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C DQPc NC VDDQ
D
DQc
DQc
VDDQ
E
DQc
DQc
VDDQ
F
DQc
DQc
VDDQ
G
DQc
DQc
VDDQ
H NC NC NC
J
DQd
DQd
VDDQ
K
DQd
DQd
VDDQ
L
DQd
DQd
VDDQ
M
DQd
DQd
VDDQ
N DQPd NC VDDQ
P NC/144M NC/72M A
R MODE
A
A
CY7C1460SV25 (1M × 36)
4 567
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC/288M
A
Document Number: 001-43804 Rev. *J
Page 5 of 31
5 Page 
CY7C1460SV25
CY7C1462SV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460SV25 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 2.5 V I/O logic level.
The CY7C1460SV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power up, the device comes
up in a reset state which does not interfere with the operation of
the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data Out (TDO)
The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in the
Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Identification Codes on page 17. Three of these instructions are
listed as RESERVED and should not be used. The other five
instructions are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
Document Number: 001-43804 Rev. *J
Page 11 of 31
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1460SV25.PDF ] | |
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