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PDF CY7C1049GN Data sheet ( Hoja de datos )
| Número de pieza | CY7C1049GN | |
| Descripción | 4-Mbit (512K words x 8 bit) Static RAM | |
| Fabricantes | Cypress | |
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CY7C1049GN
4-Mbit (512K words × 8 bit) Static RAM
4-Mbit (512K words × 8 bit) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active and standby currents
❐ Active current: ICC = 38 mA typical
❐ Standby current: ISB2 = 6 mA typical
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Pb-free 36-pin SOJ and 44-pin TSOP II packages
Functional Description
CY7C1049GN is a high-performance CMOS fast static RAM
device organized as 512K words by 8-bits.
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O7 and address on A0 through A18 pins.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O7).
All I/Os (I/O0 through I/O7) are placed in a high-impedance state
during the following events:
■ The device is deselected (CE HIGH)
■ The control signal OE is de-asserted
The logic block diagram is on page 2.
Product Portfolio
Product
CY7C1049GN18
CY7C1049GN30
CY7C1049GN
Range
Industrial
VCC Range (V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
Speed
(ns)
10/15
15
10
10
Power Dissipation
Operating ICC, (mA)
f = fmax
Typ[1]
Max
Standby, ISB2 (mA)
Typ[1]
Max
– 40
38 45
6
8
38 45
Notes
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-10613 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 12, 2016
1 page  
Pin Configurations (continued)
Figure 2. 44-pin TSOP II pinout, Single Chip Enable [3]
NC
NC
A0
A1
A2
A3
A4
/CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
/WE
A5
A6
A7
A8
A9
NC
NC
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 44-pin TSOP II 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
NC
NC
NC
A18
A17
A16
A15
/OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
CY7C1049GN
Notes
3. NC pins are not connected internally to the die.
Document Number: 002-10613 Rev. *A
Page 5 of 18
5 Page 
CY7C1049GN
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (CE Controlled) [18, 19]
ADDRESS
CE
WE
tS A
tA W
tW C
tS C E
tPW E
tH A
B H E/
BLE
tB W
OE
D A T A I/O
ADDRESS
CE
tHZOE
tS D
tH D
D A T AIN V A L I D
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18, 19, 20]
tW C
tSCE
BHE /
BLE
WE
DATA I /O
tSA
tBW
tAW
t HZWE
tPWE
tH A
t LZW E
tSD tHD
D A TA IN V A LID
Notes
18. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
20. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
Document Number: 002-10613 Rev. *A
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY7C1049GN.PDF ] | |
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