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Número de pieza | PI6C557-10 | |
Descripción | Network Clock Generator | |
Fabricantes | Pericom Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PI6C557-10 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! Product Features
• 100MHz Differential Output, 33MHz LVCMOS
• Supply voltage of 3.3V ±5%
• 25MHz input frequency
• Jitter 60ps cycle-to-cycle (typ) 100MHz
• Industrial temperature range
• Packaging: (Pb-free and Green)
—16-pin, 173 mils wide TSSOP
Block Diagram
PI6C557-10
Network Clock Generator
Description
The PI6C557-10 is an integrated 100MHz differential and 33MHz
LVCMOS clock generator. It uses a 25MHz quartz crystal to provide
an input frequency reference. The high performance internal PLL
multiplier is a proven design that ships world-wide for PCI Express
applications.
The PI6C557-10 is available in a 16 lead 4.4 x 5.0mm TSSOP
package and is operated from a single 3.3V supply. Separate supply
pins are provided for analog core, 100MHz differential output,
and 33MHz LVCMOS output to adhere to lowest risk, best known
power supply partitioning practices.
VDD
5
X1/CLK
25 MHz
crystal or clock X2
Load
Capacitors
Phase Lock Loop
Crystal
Driver
5
GND
OE
100M
100M
33M
Pin Configuration
09-0015
GNDA
VDDA
VDDX
XIN
XOUT
GNDX
GND
VDD
1
2
3
4
5
6
7
8
1
16 OE
15 GND
14 100M
13 100M
12 VDD
11 VDD33
10 33M
9 GND33
PS8982A
07/27/09
1 page Thermal Characteristics
Symbol
θJA
θJC
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Conditions
Still air
Recomended Crystal Specification
Pericom recommends SRX7278 for optimium performance.
Parameter
Value
Mode of Oscillation
Frequency
Frequency Tolerance
Temperature and Aging Stability
Load Cap
Equivelent Series Resistance
Drive Level
Fundamental AT
25
±20
±30
20
35
100
Units
MHz
PPM
pF
Ω
μW
PI6C557-10
Network Clock Generator
Min.
Typ. Max.
90
24
Unit
°C/W
°C/W
3.3V Differential Driver Termination
3.3V
Driver
50Ω
50Ω
R1
100Ω
3.3V
100Ω Differential Transmission Line
A general interface is shown above. In a 100 differential transmission line environment, drivers require a
matched load termination of 100 across near the receiver input.
09-0015
5
PS8982A
07/27/09
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet PI6C557-10.PDF ] |
Número de pieza | Descripción | Fabricantes |
PI6C557-10 | Network Clock Generator | Pericom Semiconductor |
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