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Número de pieza | MUN5136DW1T1G | |
Descripción | Dual PNP Bias Resistor Transistors | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! MUN5136DW1,
NSBA115EDXV6
Dual PNP Bias Resistor
Transistors
R1 = 100 kW, R2 = 100 kW
PNP Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
• S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Rating
Symbol
Max
Unit
Collector−Base Voltage
VCBO
50
Vdc
Collector−Emitter Voltage
VCEO
50
Vdc
Collector Current − Continuous
IC 100 mAdc
Input Forward Voltage
VIN(fwd)
40
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device
Package
Shipping†
MUN5136DW1T1G
SOT−363
3,000 / Tape & Reel
NSBA115EDXV6T1G
SOT−563
4,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
http://onsemi.com
PIN CONNECTIONS
(3) (2) (1)
R1
Q1
R2 R1
(4) (5)
R2
Q2
(6)
MARKING DIAGRAMS
6
0N M G
G
1
SOT−363
CASE 419B
0N M G
1G
SOT−563
CASE 463A
0N = Specific Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 1
1
Publication Order Number:
DTA115ED/D
1 page MUN5136DW1, NSBA115EDXV6
PACKAGE DIMENSIONS
E
2X
bbb H D
e
6X ccc C
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
D
A
aaa H D
D
6 54
E1
L2
1 23
aaa C
2X 3 TIPS
H
L
DETAIL A
GAGE
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
B
TOP VIEW
6X b
ddd M C A-B D
A2
A
DETAIL A
A1
SIDE VIEW
C
SEATING
PLANE
c
END VIEW
MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOM MAX
A −−− −−− 1.10 −−− −−− 0.043
A1 0.00 −−− 0.10 0.000 −−− 0.004
A2 0.70 0.90 1.00 0.027 0.035 0.039
b 0.15 0.20 0.25 0.006 0.008 0.010
C 0.08 0.15 0.22 0.003 0.006 0.009
D 1.80 2.00 2.20 0.070 0.078 0.086
E 2.00 2.10 2.20 0.078 0.082 0.086
E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 BSC
0.026 BSC
L 0.26 0.36 0.46 0.010 0.014 0.018
L2 0.15 BSC
0.006 BSC
aaa 0.15
0.006
bbb 0.30
0.012
ccc 0.10
0.004
ddd 0.10
0.004
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
6X
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
5 Page |
Páginas | Total 6 Páginas | |
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