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PDF PI6C4911510-05 Data sheet ( Hoja de datos )
| Número de pieza | PI6C4911510-05 | |
| Descripción | 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6C4911510-05
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer with Sync OE
Features
ÎÎFMAX < 1.5GHz
ÎÎ10 pairs of differential LVPECL/ ECL outputs
ÎÎLow additive jitter, < 0.03ps (typ)
ÎÎSelectable differential input pairs with single ended input
option
ÎÎInput CLK accepts: LVPECL, LVDS, CML, SSTL input level
ÎÎOutput skew: 55ps (max)
ÎÎOperating Temperature: -40oC to 85oC
ÎÎECL mode operating voltage range
VDD/ VDDO = 0V, VEE = -3.6V to -2.375V
ÎÎPower supply: 3.3V ±10% or 2.5V ±5%
ÎÎPackaging (Pb-free & Green), 32-pin TQFP available
Description
The PI6C4911510-05 is a high-performance low-skew 1-to-10 LVPE-
CL/ECLfanout buffer. The PI6C4911510-05 features two selectable
differentialclockinputsandtranslatestotenLVPECL/ECLoutputs.
The CLK inputs accept LVPECL, LVDS, CML and SSTL signals.
PI6C4911510-05 is ideal for clock distribution applications such
as providing fanout for low noise Pericom oscillators.
Block Diagram
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
SYNC_OE
0
1
D
Q
LE
13-0151
Q0+
Q0-
Q1+
Q1-
Q2+
Q2-
Q3+
Q3-
Q4+
Q4-
Q5+
Q5-
Q6+
Q6-
Q7+
Q7-
Q8+
Q8-
Q9+
Q9-
Pin Configuration
VDD 1
CLK_SEL 2
CLK0 3
nCLK0 4
SYNC_OE 5
CLK1 6
nCLK1 7
VEE 8
24 Q3+
23 Q3-
22 Q4+
21 Q4-
20 Q5+
19 Q5-
18 Q6+
17 Q6-
1 PI6C4911510-05 Rev C 10/09/2013
1 page  
PI6C4911510-05
2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to
LVPECL Fanout Buffer w/ Sync OE
LVPECL DC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%)
Symbol
IIH
IIL
VPP
VCMR
Parameter
Input High
Current
CLK0, CLK1
nCLK0, nCLK1
Input Low Cur- CLK0, CLK1
rent nCLK0, nCLK1
Peak-to-peak Voltage
Common Mode Input Voltage(1)
Conditions
VIN = VDD = 3.6V
VIN = VDD = 3.6V
VDD = 3.6V, VIN = 0V
VDD = 3.6V, VIN = 0V
Min Typ
-150
-150
0.4
VEE+0.5
Max
150
150
0.8
VDD- 0.85
Units
µA
µA
µA
µA
V
V
VOH
Output High Voltage(2)
VDDO = 2.5V or 3.3V
VDDO-1.4 VDDO-0.9 V
VOL Output Low Voltage(2)
VDDO = 2.5V or 3.3V
VDDO-2.0 VDDO-1.7 V
VSWING Peak-to-peak Output Voltage Swing
0.6 1.0 V
R Input Pullup/Pulldown Resistance
50 kΩ
Notes:
1. For single-ended applications, the maximum input voltage for CLK and /CLK is VDD+0.3V
2. Outputs terminated with 50Ω to VDD-2.0V
AC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%)
Symbol Parameter
Conditions
Min Typ
Max
fmax
tpd
Tsk
Tsk(p-p)
Output Frequency
Propagation Delay(1)
Output-to-output Skew(2)
Part-to-Part Skew(3)
1500
1200 2100
40 55
250
tr/tf Output Rise/Fall time
todc Output duty cycle
VPP Output Swing
20% - 80%
f ≤ 650 MHz
LVPECL outputs,
f ≤ 650 MHz
150
48
400
52
tj
Buffer additive jitter RMS
156.25MHz with 12KHz to
20MHz integration range
0.03
Notes:
1. Measured from the differential input to the differential output crossing point
2. Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point
3. This parameter is guaranteed by design
Units
MHz
ps
ps
ps
ps
%
mV
ps
13-0151
5 PI6C4911510-05 Rev C 10/09/2013
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6C4911510-05.PDF ] | |
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