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PDF PI6C4911506-06 Data sheet ( Hoja de datos )
| Número de pieza | PI6C4911506-06 | |
| Descripción | Crystal/LVCMOS/Differential - LVPECL Fanout Buffer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6C4911506-06
Low Skew, 1-To-6, Crystal/LVCMOS/Differential -
3.3V, 2.5V LVPECL Fanout Buffer
Features
ÎÎ6 LVPECL outputs
ÎÎUp to 1.5GHz output frequency
ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential
156.25MHz, 12KHz to 20MHz integration range)
ÎÎSelectable reference inputs support either single-ended
or differential or Xtal
ÎÎLow skew between outputs within banks (<40ps)
ÎÎLow delay from input to output (Tpd typ. 1.5ns)
ÎÎSeparate Input output supply voltage for level shifting
ÎÎ2.5V / 3.3V power supply
ÎÎIndustrial temperature support
ÎÎTSSOP-24 package
Description
The PI6C4911506-06 is a high performance LVPECL fanout
buffer device that accepts crystal, single ended and differential
inputs. The part supports up to 1.5GHz frequency. This device is
ideal for systems that need to distribute low jitter clock signals to
multiple destinations.
Block Diagram
Pin Configuration (24-Pin TSSOP)
CLK_EN Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
XTAL_IN
XTAL_OUT
OSC
CLK0 Pulldown
CLK1 Pulldown
nCLK1 Pullup
00
01
1X
D
Q
LE
Q0
nQ0
6 LVPECL Outputs
Q5
nQ5
nQ2
Q2
VDD
nQ1
Q1
VEE
nQ0
Q0
CLK_SEL0
XTAL_IN
XTAL_OUT
CLK_EN
1
2
3
4
5
6
7
8
9
10
11
12
24 Q3
23 nQ3
22 VDD
21 Q4
20 nQ4
19 VDD
18 Q5
17 nQ5
16 CLK_SEL1
15 nCLK1
14 CLK1
13 CLK0
12-0290
1 www.pericom.com PI6C4911506-06 RevA 11/02/2012
1 page  
PI6C4911506-06
Low Skew, 1-To-6, Crystal/LVCMOS/Differantial -
3.3V, 2.5V LVPECL Fanout Buffer
AC Characteristics, VDD = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
fMAX
tPD
tjit
tsk(o)
tsk(pp)
Parameter
Test Condition
Output Frequency
CLK1/nCLK1
CLK0
Propagation Delay 1A, 1B
CLK1/nCLK1, 156.25MHz,
Buffer Additive Jitter, RMS
Integration Range:
12kHz - 20MHz
Output Skew 2
Part-to-Part Skew 3
Min.
Typ.
1.5
0.03
Max.
1500
300
Units
MHz
ns
ps
55 ps
450 ps
tR / tP
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
120
48
350 ps
52 %
AC Characteristics, VDD = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
fMAX
tPD
tjit
tsk(o)
Parameter
Test Condition
Output Frequency
CLK1/nCLK1
CLK0
Propagation Delay 1A, 1B
CLK1/nCLK1, 156.25MHz,
Buffer Additive Jitter, RMS
Integration Range:
12kHz - 20MHz
Output Skew 2
Min.
Typ.
1.5
0.03
Max.
1500
300
Units
MHz
ns
ps
55 ps
tsk(pp)
Part-to-Part Skew3
450 ps
tR / tP
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
120
48
350 ps
52 %
Note:
1A. Measured from the differential input crossing point to the differential output crossing point.
1B.
2.
Measured
Defined as
from
skew
VbeDtDw/e2einnpouuttpcurotsssaitntghpeosianmt etosuthpepldyifvfoerlteangteiaalnodutwpiutthcerqoussailnlgoapdoicnotn. ditions.
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
12-0290
5 www.pericom.com PI6C4911506-06 RevA 11/02/2012
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6C4911506-06.PDF ] | |
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