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PDF PI6C59S6005 Data sheet ( Hoja de datos )
| Número de pieza | PI6C59S6005 | |
| Descripción | 6 GHz Selectable Fanout Buffer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6C59S6005
6 GHz Selectable Fanout Buffer with Internal Termination
Features
ÎÎInput Clock Frequency up to 6 GHz Typical
ÎÎ5 pairs of differential LVPECL/ CML outputs
ÎÎLow additive jitter, < 0.05ps (max)
ÎÎInput CLK accepts: LVPECL, LVDS, CML, SSTL input level
ÎÎOutput to Output skew: <20ps
ÎÎOperating Temperature: -40oC to 85oC
ÎÎPower supply: 3.3V ±10% or 2.5V ±5%
ÎÎPackaging (Pb-free & Green)
ÎÎ24-pin TQFN available
Description
The PI6C59S6005 is a high-performance low-skew 1-to-5 LVPECL
fanout buffer. The CLK inputs accept LVPECL, LVDS, CML and
SSTL signals. PI6C59S6005 is ideal for clock distribution appli-
cations such as providing fanout for low noise Pericom oscilla-
tors.
Block Diagram
Pin Configuration
TS IS
REF_IN0+
VTH
REF_IN0-
REF_IN1+
VREF-AC
REF_IN1-
0
1
EN
D
Q
LE
OS
Q0+
Q0-
Q1+
Q1-
Q2+
Q2-
Q3+
Q3-
Q4+
Q4-
Q1+
Q1-
VDD
Q2+
Q2-
VDD
1 24 23 22 21 20 19 18
2 17
3 16
4 15
5 14
6 13
7 8 9 10 11 12
IS
REF_IN0+
VTH
VREF-AC
REF_IN0-
TS
14-0182
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PI6C59S6005 Rev B
10/27/2014
1 page  
Output Swing vs Frequency
PI6C59S6005
6 GHz Selectable Fanout Buffer with Internal Termination
14-0182
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PI6C59S6005 Rev B
10/27/2014
5 Page 
PI6C59S6005
6 GHz Selectable Fanout Buffer with Internal Termination
LVPECL Output V_swing Adjustment
It is suggested to add another cross 100ohm at TX side to tune
the LVPECL output V_swing without changing the optimal
150ohm pull-down bias in Fig. 12. This form of double termina-
tion can reduce the V_swing in ½ of the original at the RX side.
By fine tuning the 100ohm resistor at the TX side with larger
values like 150 to 200ohm, one can increase the V_swing by >
1/2 ratio.
Fig. 12 LVPECL Output V_swing Adjustment
CML AC Output Drive
CML is implemented mostly via AC coupling. With AC cou-
pling, CML can drive LVPECL and LVDS inputs as well with an
external 100 ohm equivalent differential termination.
Phase Jitter
Phase noise is short-term random noise attached on the clock
carrier and it is a function of the clock offset from the car-
rier, for example dBc/Hz@10kHz which is phase noise power
in 1-Hz normalized bandwidth vs. the carrier power @10kHz
offset. Integration of phase noise in plot over a given frequency
band yields RMS phase jitter, for example, to specify phase jitter
<=1ps at 12k to 20MHz offset band as SONET standard specifi-
cation.
PCIe Ref_CLK Jitter
PCIe reference clock jitter specification requires testing via the
PCI-SIG jitter tool, which is regulated by US PCI-SIG organiza-
tion. The jitter tool has PCIe Serdes embedded filter to calculate
the equivalent jitter that relates to data link eye closure. Direct
peak-peak jitter or phase jitter test data, normally is higher than
jitter measure using PCI-SIG jitter tool. It has high-frequency
jitter and low-frequency jitter spec. limit. For more informa-
tion, please refer to the PCI-SIG website: http://www.pcisig.com/
specifications/pciexpress/
Device Thermal Calculation
Fig. 13 shows the JEDEC thermal model in a 4-layer PCB.
0.01uF
0.01uF
Zo =100Ω
*100Ω
+IN
- IN
CML Output
CML Input
*Remove 100Ω if ASIC is
CML has termination
Clock Jitter Definitions
Total jitter= RJ + DJ
Random Jitter (RJ) is unpredictable and unbounded timing noise
that can fit in a Gaussian math distribution in RMS. RJ test val-
ues are directly related with how long or how many test samples
are available. Deterministic Jitter (DJ) is timing jitter that is pre-
dictable and periodic in fixed interference frequency. Total Jitter
(TJ) is the combination of random jitter and deterministic jitter:
, where is a factor based on total test sample count. JEDEC std.
specifies digital clock TJ in 10k random samples.
Fig. 13 JEDEC IC Thermal Model
Important factors to influence device operating temperature are:
1) The power dissipation from the chip (P_chip) is after subtract-
ing power dissipation from external loads. Generally it can be
the no-load device Idd
2) Package type and PCB stack-up structure, for example, 1oz
4 layer board. PCB with more layers and are thicker has better
heat dissipation
14-0182
11
PI6C59S6005 Rev B
10/27/2014
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI6C59S6005.PDF ] | |
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