PDF PI6CDBL402B Data sheet ( Hoja de datos )

Número de pieza	PI6CDBL402B
Descripción	4-Output Low Power PCIE GEN 1-2-3 Buffer
Fabricantes	Pericom Semiconductor
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No Preview Available ! PI6CDBL402B 4 -Output Low Power PCIE GEN 1-2-3 Buffer Features ÎÎPhase jitter filter for PCIe 3.0/ 2.0/ 1.0 application ÎÎLow power consumption with independent output power supply 1.8V~3.3V ÎÎLow skew < 60ps ÎÎLow cycle-to-cycle jitter - 45ps (typ.) @100MHz ÎÎ< 1 ps additive RMS phase jitter ÎÎOutput Enable for all outputs ÎÎProgrammable PLL Bandwidth ÎÎ100 MHz PLL Mode operation ÎÎ1 - 400 MHz Bypass Mode operation ÎÎ3.3V Operation ÎÎPackaging (Pb-free and Green): -28-Pin TSSOP (L28) Block Diagram Description Pericom Semiconductor's PI6CDBL402B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compat- ible with PCIe 1.0 and 2.0 specification. The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of PWRDWN# and SMBus, SCLK and SDA. Pin Configuration OE_INV OE_0 & OE_3 PWRDWN# Output Control SCLK SDA PLL/BYPASS# SRC SRC# SMBus Controller PLL_BW# PLL OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# VDD SRC SRC# GND VDDO OUT0 OUT0# OE_0 OUT1 OUT1# VDDO PPLLLL/B/BYYPPAASSSS# SCLK SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VDD_A 27 GNDA 26 NC 25 OE_INV 24 VDDO 23 OUT3 22 OUT3# 21 OE_3 20 OUT2 19 OUT2# 18 VDDO 17 PLL_BW# 16 VDD 15 PWRDWN# All trademarks are property of their respective owners. 15-0083 1 www.pericom.com 06/30/15 1 page PI6CDBL402B 4 -Output Low Power PCIE GEN 1-2-3 Buffer Data Byte 2: Control Register Bit Descriptions 0 Reserved 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved Type Power Up Condition Output(s) Affected Source Pin NA NA NA NA NA NA NA NA Data Byte 3: Control Register Bit Descriptions 0 1 2 3 4 Reserved 5 6 7 Type RW RW RW RW RW RW RW RW Power Up Condition Output(s) Affected Source Pin Data Byte 4: Control Register Bit Descriptions 0 1 2 3 4 Pericom ID 5 6 7 Type R R R R R R R R Power Up Condition 0 0 0 0 0 1 0 0 Output(s) Affected NA NA NA NA NA NA NA NA Source Pin NA NA NA NA NA NA NA NA All trademarks are property of their respective owners. 15-0083 5 www.pericom.com 06/30/15 5 Page PI6CDBL402B 4 -Output Low Power PCIE GEN 1-2-3 Buffer Electrical Characteristics–Current Consumption (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 3.3V+/- 10%, VDDO = 2.5V+/-10%, VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol Parameters Condition IDDOP Operating Supply Current1 Total power consumption, All outputs active @100MHz, typical value under VDDO = 1.8V Total power consumption, All outputs active @100MHz PLL bypass mode, typical value under VDDO = 1.8V IDDPD Powerdown Current1,2 Total power consumption, Outputs Low Note: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Input clock stopped. Min. Type 50 24 Max. 60 Units mA 28 mA 1.3 mA Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 3.3V+/-10%, VDDO = 2.5V+/-10%, VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol tDC tDCD tpdBYP tpdPLL tskew tjcyc-cyc Parameters Duty Cycle1 Duty Cycle Distortion1,3 Skew, Input to Output1,4 Skew, Output to Output1,2 Jitter, Cycle to cycle1,2 Condition Measured differentially, PLL Mode Measured differentially, Bypass Mode @100MHz Bypass Mode, VT = 50% PLL Mode VT = 50% PLL Mode VT = 50% PLL mode Additive Jitter in Bypass Mode Min. 45 -1.3 2500 -260 Type 0 Max. 55 1.3 5000 260 60 60 25 Note: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Measured from differential waveform 3. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4. All outputs at default slew rate 5. The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN. Units % % ps ps ps ps ps All trademarks are property of their respective owners. 15-0083 11 www.pericom.com 06/30/15 11 Page

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