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PDF PI6CFGL201B Data sheet ( Hoja de datos )
| Número de pieza | PI6CFGL201B | |
| Descripción | 2-Output Low Power PCIE Gen 1-2-3 Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6CFGL201B
2-Output Low Power PCIE Gen 1-2-3 Clock Generator
Features
ÎÎ25MHz crystal or reference clock input
ÎÎ100MHz low power HCSL or LVDS compatible outputs
ÎÎPCIe 3.0, 2.0 and 1.0 compliant
ÎÎSelectable spread spectrum of -0.25%, -0.5% and no spread
ÎÎProgrammable output amplitude and slew rate
ÎÎCycle-to-cycle jitter (typ.) ~ 30ps
ÎÎSupply voltage of 3.3V+/-10%
ÎÎOutput supply voltage of 1.8V (1.05V to 3.6V supported)
ÎÎIndustrial ambient operating temperature
ÎÎAvailable in lead-free package: 24-TQFN
Description
The PI6CFGL201B is a 2-output very low power 100MHz fre-
quency generator for PCIe Gen 1, 2 and 3 applications with inte-
grated output terminations providing Zo=100Ω. The device has
2 output enables for clock management and supports 2 different
spread spectrum levels in addtion to spread off. The device also
has one 1.8V LVCMOS REF1.8 output.
Applications
ÎÎPCIe 3.0/2.0/1.0 clock generation
Pin Configuration (24-Pin TQFN)
24 23 22 21 20 19
XTAL_IN 1
18 CLK1#
XTAL_OUT 2
17 CLK1
VDDXTAL 3
16 VDDA3.3
SADR/REF1.8 4
15 GNDA
VDDREF1.8 5
14 CLK0#
GNDDIG 6
13 CLK0
7 8 9 10 11 12
Block Diagram
XTAL_IN or Ref CLK
XTAL_OUT
OE(1:0)#
I
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
OSC
+
t
u
CONTROL
LOGIC
SS Capable PLL
All trademarks are property of their respective owners.
15-0134
www.pericom.com
1
REF1.8
+ CLK0
CLK0#
+ CLK1
CLK1#
PI6CFGL201B
RevB
03/16/16
1 page  
PI6CFGL201B
2-Output Low Power PCIE Gen 1-2-3 Clock Generator
Electrical Characteristics–Input/Supply/Common Parameters
(Based on TA = -40~85oC; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)
Symbol
VDDX
VDDO
TA
VIH
VIM
VIL
VT+
VT-
VH
VOH
Parameters
Supply Voltage1
Supply Voltage1
Ambient Operating
Temperature1
Input High Voltage1
Input Mid Voltage1
Input Low Voltage1
Schmitt Trigger Postive
Going Threshold Voltage1
Schmitt Trigger Negative
Going Threshold Voltage1
Hysteresis Voltage1
Output High Voltage1
VOL Outputt Low Voltage1
IIN
Input Current1
IINP
fin
Lpin
CIN
Cout
tSTAB
f MODIN
tLATOE#
tDRVPD
Input Frequency1
Pin Inductance1
Capacitance1
Clock output Stabiliza-
tion1, 2
Input SS Modulation
Frequency1
OE# Latency1, 3
Tdrive_PD#1, 3
Condition
Supply voltage for core, analog
Supply voltage outputs
Single-ended inputs, except SMBus, SS_EN_tri
SS_EN_tri
Single-ended inputs, except SMBus, SS_EN_tri
Single-ended inputs, except SS_EN_tri
Single-ended inputs, except SS_EN_tri
VT+ - VT-
Single-ended
-2mA
outputs,
except
SMBus.
IOH
=
Single-ended
-2mA
outputs,
except
SMBus.
IOL
=
S(eixncgllued-eenXdTedAiLn_pIuNtsp, iVnI)N = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VreIsNis=toVrsDD; Inputs with internal pull-down
XTAL, or XTAL_IN
Control Inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of CKPWRGD_
PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
CLK start after OE# assertion
CLK stop after OE# deassertion
CLK output enable after
CKPWRGD_PD# de-assertion
Min.
3.0
1.05
Type
3.3
1.8
Max.
3.6
3.3
Units
V
V
-40 25 85
°C
0.65 VDD
0.4 VDD
-0.3
0.5 VDD
VDD +0.3
0.6 VDD
0.35 VDD
V
V
V
0.6 VDD V
0.4 VDD
0.05 VDD
V-0D.4D5
0.5 VDD
0.2 VDD
V
V
V
0.45 V
-5 5 uA
-200 200
23 25 26
7
1.5 5
6
0.6 1
30 31.500 33
13
300
uA
MHz
nH
pF
pF
ms
kHz
clocks
us
All trademarks are property of their respective owners.
15-0134
www.pericom.com
5
PI6CFGL201B
RevB
03/16/16
5 Page 
PI6CFGL201B
2-Output Low Power PCIE Gen 1-2-3 Clock Generator
SMBus Table: REF1.8 Control Register
BYTE 3
Bit Name
7
6
REF1.8
5
REF1.8 Power Down
Function
4 REF1.8 OE
3 Reserved
2 Reserved
1 Reserved
0 Reserved
Control Function
Slew Rate Control
Type
RW
RW
Wake-ON-LAN Enable for REF1.8 RW
REF1.8 Output Enable
RW
0
00 = 0.9V/ns
10 = 1.6V/ns
REF1.8 does not
run in Power
Down
Low
1
01 =1.3V/ns
11 = 1.8V/ns
REF1.8 runs in
Power Down
Enabled
Default
0
1
0
1
1
1
1
1
Byte 4 is reserved and reads back 'hFF'.
SMBus Table: Revision and Vendor ID Register
BYTE 5
Bit Name
7 RID3
6 RID2
5 RID1
4 RID0
3 VID3
2 VID2
1 VID1
0 VID0
Control Function
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
0
A rev = 0000
1
Default
0
0
0
0
0
0
0
0
All trademarks are property of their respective owners.
15-0134
www.pericom.com
11
PI6CFGL201B
RevB
03/16/16
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet PI6CFGL201B.PDF ] | |
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