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PDF PI6CFGL202B Data sheet ( Hoja de datos )
| Número de pieza | PI6CFGL202B | |
| Descripción | Low Power PCIe 3.0 Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Features
ÎÎPCIe® 3.0, 2.0 and 1.0 compliant
ÎÎLVDS compatible outputs
ÎÎSupply voltage of 3.3V ±10%
ÎÎ25MHz crystal or clock input frequency
ÎÎLow power consumption with independent output power
supply 1.05V to 3.3V
ÎÎJitter 35ps cycle-to-cycle (typ)
ÎÎSpread of -0.5%, -0.75%, and no spread
ÎÎIndustrial temperature range
ÎÎSpread Bypass option available
ÎÎSpread and frequency selection via external pins
ÎÎPackaging: (Pb-free and Green)
àà 16-pin TSSOP (L16)
Description
The PI6CFGL202B is a spread spectrum clock generator compli-
ant to PCI Express® 3.0 and Ethernet requirements. The device is
used for PC or embedded systems to substantially reduce Electro-
magnetic Interference (EMI).
The PI6CFGL202B provides two differential (HCSL) or LVDS
spread spectrum outputs. The PI6CFGL202B is configured to se-
lect spread and clock selection. Using Pericom's patented Phase-
Locked Loop (PLL) techniques, the device takes a 25MHz crystal
input and produces two pairs of differential outputs (HCSL) at
25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It
also provides spread selection of -0.5%, -0.75%, and no spread.
Block Diagram
Pin Configuration (16-Pin TSSOP)
VDD
2
SS1:SS0
2
S1:S0
2
XTAL_IN or Ref CLK
25 MHz
crystal or clock
XTAL_OUT
Pulling
Capacitors
Control
Logic
Phase
Lock
Loop
Crystal
Driver
2
GND
OE
S0 1
CLK0 S1 2
CLK0 SS0 3
XTAL_IN 4
XTAL_OUT 5
CLK1
CLK1
OE 6
GNDX 7
SS1 8
16 VDDA3.3
15 CLK0
14 CLK0#
13 GNDA
12 VDDO
11 CLK1
10 CLK1#
9 VDDDIG3.3
All trademarks are property of their respective owners.
15-0025
1
www.pericom.com 03/03/15
PI6C557-03B
1 page  
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Symbol
f MODIN
TOE
tOT
tSTABLE
tSPREAD
Parameters
Input SS Modulation
Frequency1
Output Enable Time1
Output Disable Time1
From Power-up to
VDD=3.3V1
Setting period after
spread change1
Condition
Allowable Frequency
(Triangular Modulation)
All output
All output
From Power-up VDD=3.3V
Setting period after spread change
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance
3. Time from deassertion until outputs are >200 mV
4. DIF_IN input
Min. Typ. Max. Units
30 31.500 33
kHz
10 μs
10 μs
3.0 ms
3.0 ms
Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs (TA = -40~85oC; VDD = 3.3V+/-
10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol Parameters
Condition
Min. Typ. Max. Units
Trf Slew rate1,2,3
1.1 2 4.5 V/ns
VHIGH
VLOW
Voltage High1
Voltage Low1
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averag-
ing on)
660
-150
950 mV
150 mV
Vmax
Max Voltage1
Measurement on single ended signal using
1150 mV
Vmin
Min Voltage1
absolute value. (Scope averaging off)
-300
mV
Vswing
Vswing1,2
Scope averaging off
300 mV
Vcross_abs Crossing Voltage (abs)1,5 Scope averaging off
250 550 mV
Δ-Vcross
Crossing Voltage (var)1,6 Scope averaging off
140 mV
tDC Duty Cycle1
Measured differentially, PLL Mode
45 55 %
tskew Skew, Output to Output1 VT = 50%
50 ps
tjcyc-cyc
Jitter, Cycle to cycle1,2
PLL mode @100MHz output, SSC off
50 ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform
3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.
4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point
where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula-
tions.
5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is
to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
All trademarks are property of their respective owners.
15-0025
5
www.pericom.com 03/03/15
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PI6CFGL202B.PDF ] | |
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