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PDF PI6CFGL402B Data sheet ( Hoja de datos )
| Número de pieza | PI6CFGL402B | |
| Descripción | Low Power PCIe 3.0 Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6CFGL402B
Low Power PCIe 3.0 Clock Generator with 4 HCSL Outputs
Features
• PCIe® 3.0, 2.0 and 1.0 complaint
• LVDS compatible outputs
• Supply voltage of 3.3V ±5%
• 25MHz crystal or clock input frequency
• Low power consumption with independent output power
supply 1.05V to 3.3V
• Jitter 40ps cycle-to-cycle (typ)
• Spread of -0.5%, -1.0%, -1.5%, and no spread
• Industrial temperature range
• Spread Bypass option available
• Spread and frequency selection via external pins
• Packaging: (Pb-free and Green)
→20-pin, 173-mil wide TSSOP
Description
The PI6CFGL402B is a spread spectrum clock generator
compliant to PCI Express® 3.0 and Ethernet requirements.
The device is used for PC or embedded systems to substantially
reduce Electromagnetic Interference (EMI).
The PI6CFGL402B provides four differential (HCSL) or LVDS
spread spectrum outputs. The PI6CFGL402B is configured
to select spread and clock selection. Using Pericom's patented
Phase-Locked Loop (PLL) techniques, the device takes a 25MHz
crystal input and produces four pairs of differential outputs
(HCSL) at 100MHz and 200MHz clock frequencies. It also
provides spread selection of -0.5%, -1.0%, -1.5%, and no spread.
Block Diagram
VDD PD OE
2
S[2:0] 3
Spread
Spectrum/
Output
clock
selection
SS Circuitry
25 MHzX1/CLK
crystal
or clock X2
Crystal
Driver
PCualpliancgitors
PLL
2
GND
Pin Configuration
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
VDDA3.3
S0
S1
S2
X1
X2
PD
OE
GNDXD
VDDDIG3.3
1
2
3
4
5
6
7
8
9
10
20 CLK0
19 CLK0
18 CLK1
17 CLK1
16 GNDA
15 VDDO
14 CLK2
13 CLK2
12 CLK3
11 CLK3
All trademarks are property of their respective owners.
15-0032
1
www.pericom.com 03/03/15
1 page  
PI6CFGL402B
Low Power PCIe 3.0 Clock Generator with 4 HCSL Outputs
Symbol
TSTAB
f MODIN
tOE
tOT
tSTABLE
tSPREAD
Parameters
Clk Stabilization1,2
Input SS Modulation
Frequency1
Output Enable Time1
Output Disable Time1
From power-up to
VDD = 3.3V1
Setting period after
spread change1
Condition
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
All outputs
All outputs
From Power-up VDD = 3.3V
Setting period after spread change
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance
3. Time from deassertion until outputs are >200 mV
4. DIF_IN input
Min.
Type Max. Units
0.6 1
ms
30
31.500 33
kHz
10 μs
10 μs
3.0 ms
3.0 ms
Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs (TA = -40~85oC; Supply Voltage VDD
= 3.3V +/-10%; VDDO = 1.8V +/-10%; 100MHz output frequency, See Test Loads for Loading Conditions)
Symbol
Trf
VHIGH
VLOW
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
tDC
tskew
tjcyc-cyc
Parameters
Slew rate1,2,3
Voltage High1
Voltage Low1
Max Voltage1
Min Voltage1
Vswing1,2
Crossing Voltage (abs)1,5
Crossing Voltage (var)1,6
Duty Cycle1
Skew, Output to Output1
Jitter, Cycle to cycle1,2
Condition
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope aver-
aging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
Measured differentially, PLL Mode
VT = 50%
PLL mode
Min.
1.1
660
-150
-300
300
250
45
Type
2
Max.
4.5
900
150
1150
550
140
55
50
50
Units
V/ns
mV
mV
mV
mV
mV
mV
mV
%
ps
ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform
3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.
4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point
where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula-
tions.
5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is
to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
All trademarks are property of their respective owners.
15-0032
5
www.pericom.com 03/03/15
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PI6CFGL402B.PDF ] | |
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