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PDF PI6CFGL601B Data sheet ( Hoja de datos )
| Número de pieza | PI6CFGL601B | |
| Descripción | 6-Output Low Power PCIE Gen 1-2-3 Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6CFGL601B
6-Output Low Power PCIE Gen 1-2-3 Clock Generator
Features
ÎÎ25MHz crystal or reference clock input
ÎÎ100MHz low power HCSL or LVDS compatible outputs
ÎÎPCIe 3.0, 2.0 and 1.0 compliant
ÎÎSelectable spread spectrum of -0.5% and no spread
ÎÎProgrammable output amplitude
ÎÎCycle-to-cycle jitter (typ.) ~ 30ps
ÎÎSupply voltage of 3.3V+/-10%
ÎÎOutput supply voltage of 1.8V
ÎÎIndustrial ambient operating temperature
ÎÎAvailable in lead-free package: 32-TQFN
Description
The PI6CFGL601B is a 6-output low-power 100MHz clock
sythesizer for PCIe Gen 1-2-3. It runs from a 25MHz XTAL,
provides spread spectrum capability, and has an SMBus for
software control of the device.
Application
ÎÎPCIe 3.0/2.0/1.0 clock generation
Pin Configuration
32 31 30 29 28 27 26 25
NC 1
VDD 2
24 SDATA
23 SCLK
NC 3
22 GND
GND 4
21 CLK_5
GND 5
20 CLK_5#
CLK_0 6
19 VDDO1.8
CLK_0# 7
18 CLK_4
VDDO1.8 8
17 CLK_4#
9 10 11 12 13 14 15 16
Block Diagram
XTAL_IN or Ref CLK
XTAL_OUT
I+
SDATA
SCLK
OSC
-
+
t
u
CONTROL
LOGIC
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
6
+
CLK(5:0)
100MHz
All trademarks are property of their respective owners.
15-0018
1
PI6CFGL601B RevA 01/16/15
1 page  
PI6CFGL601B
6-Output Low Power PCIE Gen 1-2-3 Clock Generator
SMBus Table: Output Enable Register
BYTE 3
Bit Pin#
7
6
5
4
3
2
1
0
Name
CLK_5 OE
CLK_4 OE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Output Enable
Output Enable
SMBus Table: Reserved Register
BYTE 4
Bit Pin#
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
SMBus Table: Output amplitude adjustment
BYTE 5
Bit Pin#
7
6
5
4
3
2
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
1
CLK_0/1/2/3/4/5
AMP
Amplitude adjustment
0
Type
R/W
R/W
0
Disable
Disable
1
Enable
Enable
Type 0
1
Type 0
1
R/W
R/W
00=700mV
01=800mV
10=900mV
11=1000mV
Default
1
1
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
1
All trademarks are property of their respective owners.
15-0018
5
PI6CFGL601B RevA 01/16/15
5 Page 
Test Loads
PI6CFGL601B
6-Output Low Power PCIE Gen 1-2-3 Clock Generator
Low-Power HCSL Differential Output Test Load
Device
Rs = 33Ω
Rs = 33Ω
5 inches
Zo=100Ω
2pF 2pF
Driving LVDS
Driving LVDS
Device
RO
Cc
Rs
Rs Cc
3.3V
R7a
Zo
R8a
R7b
R8b
LVDS Clock
input
R
Driving LVDS inputs with the PI6CFGL601B
Value
Component
R7a, R7b
R8a, R8b
Cc
Vcm
Receiver has termination
10K Ω
5.6K Ω
0.1 uF
1.2 V
Receiver does not have termination
140 Ω
75 Ω
0.1 uF
1.2 V
All trademarks are property of their respective owners.
15-0018
11
PI6CFGL601B RevA 01/16/15
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI6CFGL601B.PDF ] | |
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