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PDF MCP14A0153 Data sheet ( Hoja de datos )
| Número de pieza | MCP14A0153 | |
| Descripción | 1.5A Dual MOSFET Driver | |
| Fabricantes | Microchip | |
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MCP14A0153/4/5
1.5A Dual MOSFET Driver
with Low Threshold Input And Enable
Features
• High Peak Output Current: 1.5A (typical)
• Wide Input Supply Voltage Operating Range:
- 4.5V to 18V
• Low Shoot-Through/Cross-Conduction Current in
Output Stage
• High Capacitive Load Drive Capability:
- 1000 pF in 11.5 ns (typical)
• Short Delay Times: 25 ns (tD1), 24 ns (tD2) (typical)
• Low Supply Current: 750 µA (typical)
• Low-Voltage Threshold Input and Enable with
Hysteresis
• Latch-Up Protected: Withstands 500 mA Reverse
Current
• Space-Saving Packages:
- 8-Lead MSOP
- 8-Lead SOIC
- 8-Lead 2x3 TDFN
Applications
• Switch Mode Power Supplies
• Pulse Transformer Drive
• Line Drivers
• Level Translator
• Motor and Solenoid Drive
Package Types
MSOP/SOIC
MCP14A0153
MCP14A0155
MCP14A0154
EN A 1
IN A 2
GND 3
IN B 4
8 EN B
7 OUT A
6 VDD
5 OUT B
OUT A
OUT B
OUT A
OUT B
General Description
The MCP14A0153/4/5 devices are high-speed dual
MOSFET drivers that are capable of providing up to
1.5A of peak current while operating from a single 4.5V
to 18V supply. There are three output configurations
available; dual inverting (MCP14A0153), dual
noninverting (MCP14A0154) and complementary
(MCP14A0155). These devices feature low
shoot-through current, matched rise and fall times, and
short propagation delays which make them ideal for
high switching frequency applications.
The MCP14A0153/4/5 family of devices offer
enhanced control with Enable functionality. The
active-high Enable pins can be driven low to drive the
corresponding outputs of the MCP14A0153/4/5 low,
regardless of the status of the Input pin. An integrated
pull-up resistor allows the user to leave the Enable pins
floating for standard operation.
These devices are highly latch-up resistant under any
condition within their power and voltage ratings. They
can accept up to 500 mA of reverse current being
forced back into their outputs without damage or logic
upset. All terminals are fully protected against
electrostatic discharge (ESD) up to 2 kV (HBM) and
200 V (MM).
2×3 TDFN *
MCP14A0153 MCP14A0155
MCP14A0154
EN A 1
8 EN B
IN A 2 EP 7 OUT A
GND 3 9 6 VDD
IN B 4
5 OUT B
OUT A
OUT B
OUT A
OUT B
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2015 Microchip Technology Inc.
DS20005470A-page 1
1 page  
MCP14A0153/4/5
DC CHARACTERISTICS (OVER OPERATING TEMPERATURE RANGE) (Note 1)
Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V.
Parameters
Sym.
Min. Typ. Max. Units
Conditions
Switching Time (Note 1)
Rise Time
Fall Time
Delay Time
tR
tF
tD1
tD2
— 14 21 ns VDD = 18V, CL = 1000 pF,
TA = +125°C, see Figure 4-1,
Figure 4-2
— 13 20 ns VDD = 18V, CL = 1000 pF,
TA = +125°C, see Figure 4-1,
Figure 4-2
— 28 35 ns VDD = 18V, VIN = 5V, TA = +125°C,
see Figure 4-1, Figure 4-2
— 27 34
VDD = 18V, VIN = 5V, TA = +125°C,
see Figure 4-1, Figure 4-2
Power Supply
Supply Voltage
VDD 4.5 — 18
IDD — — 1520
Power Supply Current
IDD — — 1560
IDD — — 1560
IDD — — 1600
Note 1: Tested during characterization, not production tested.
V
µA VIN = 3V, VEN = 3V
µA VIN = 0V, VEN = 3V
µA VIN = 3V, VEN = 0V
µA VIN = 0V, VEN = 0V
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V.
Parameter
Sym. Min. Typ. Max. Units Comments
Temperature Ranges
Specified Temperature Range
Maximum Junction Temperature
Storage Temperature Range
TA -40 — +125 °C
TJ — — +150 °C
TA -65 — +150 °C
Package Thermal Information
Junction-to-Ambient Thermal Resistance, 8LD MSOP
JA — 158 — °C/W Note 1
Junction-to-Ambient Thermal Resistance, 8LD SOIC
JA — 99.8 — °C/W Note 1
Junction-to-Ambient Thermal Resistance, 8LD TDFN
JA — 53.7 — °C/W Note 1
Junction-to-Top Characterization Parameter, 8LD MSOP
JT — 2.4 — °C/W Note 1
Junction-to-Top Characterization Parameter, 8LD SOIC
JT — 5.9 — °C/W Note 1
Junction-to-Top Characterization Parameter, 8LD TDFN
JT — 0.5 — °C/W Note 1
Junction-to-Board Characterization Parameter, 8LD MSOP JB — 115.2 — °C/W Note 1
Junction-to-Board Characterization Parameter, 8LD SOIC JB — 64.8 — °C/W Note 1
Junction-to-Board Characterization Parameter, 8LD TDFN JB — 24.4 — °C/W Note 1
Note 1: Parameter is determined using a High K 2S2P 4-Layer board as described in JESD 51-7, as well as
JESD 51-5 for packages with exposed pads.
2015 Microchip Technology Inc.
DS20005470A-page 5
5 Page 
MCP14A0153/4/5
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP14A0153, MCP14A0153, MCP14A0153
2x3 TDFN
1
2
3
4
5
6
7
8
EP
MSOP/SOIC
1
2
3
4
5
6
7
8
—
Symbol
EN A
IN A
GND
IN B
OUT B/OUT B
VDD
OUT A/OUT A
EN B
EP
Description
Enable - Channel A
Input - Channel A
Device Ground
Input - Channel B
Output - Channel B
Supply Input
Output - Channel A
Enable - Channel B
Exposed Thermal Pad (GND)
3.1 Output Pins (OUT A/OUT A,
OUT B/OUT B)
The outputs are CMOS push-pull circuits that are
capable of sourcing and sinking 1.5A of peak current
(VDD = 18V). The low output impedance ensures the
gate of the external MOSFET stays in the intended
state even during large transients. This output also has
a reverse current latch-up rating of 500 mA.
3.2 Device Ground Pin (GND)
GND is the device return pin for the input and output
stages. The GND pin should have a low-impedance
connection to the bias supply source return. When the
capacitive load is being discharged, high peak currents
will flow through the ground pin.
3.3 Device Enable Pins (EN A,EN B)
The MOSFET driver device enable pins are
high-impedance inputs featuring low threshold levels.
The enable inputs also have hysteresis between the
high and low input levels, allowing them to be driven
from slow rising and falling signals and to provide noise
immunity. Driving the enable pins below the threshold
will disable the corresponding output of the device,
pulling OUT/OUT low, regardless of the status of the
Input pin. Driving the enable pins above the threshold
allows normal operation of the OUT/OUT pin based on
the status of the Input pin. The enable pins utilize
internal pull up resistors, allowing the pins to be left
floating for standard driver operation.
3.4 Control Input Pins (IN A,IN B)
The MOSFET driver control inputs are high-impedance
inputs featuring low threshold levels. The Inputs also
have hysteresis between the high and low input levels,
allowing them to be driven from slow rising and falling
signals and to provide noise immunity.
3.5 Supply Input Pin (VDD)
VDD is the bias supply input for the MOSFET driver and
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local capacitor. This bypass
capacitor provides a localized low-impedance path for
the peak currents that are provided to the load.
3.6 Exposed Metal Pad Pin (EP)
The exposed metal pad of the TDFN package is
internally connected to GND. Therefore, this pad
should be connected to a Ground plane to aid in heat
removal from the package.
2015 Microchip Technology Inc.
DS20005470A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP14A0153.PDF ] | |
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